Figure 2 illustrates the
corresponding band diagrams of the studied device at equilibrium (the solid lines) and under applied bias (the dashed line) conditions. Due to the presented conduction-band discontinuity ( Δ EC) and valance-band discontinuity (ΔEV) at the InGaP/GaAs heterointerface, the n+-GaAs/p+-InGaP/n-GaAs camel-like gate provides a larger barrier height which improves the carrier confinement as compared with the n+-GaAs/
p+-GaAs/n-GaAs homojunction camel diode. When a bias is applied to the device, as shown by the dashed lines in Fig. 2, the ΔEC about of 200 meV at p+-InGaP/n-GaAs heterointerface can effectively confine electrons in the channel at forward bias regime. Hence a higher turn-on voltage is obtained and leakage current is suppressed. On the other hand, the ΔEV about of 300 meV can prevent holes, generated by impact ionization at high drain-source voltage, injecting toward the gate electrode. Thus the leakage current and breakdown voltage can be reduced and improved, respectively. In addition, the undoped InGaAs layer and inverted delta-doped sheet are used as the active channel and carrier supply layer, respectively. When carriers transferring from the inverted delta-doped sheet to InGaAs channel, good carrier confinement may be expected. The leakage current is then decreased further. Therefore, the degradation of device properties including breakdown voltage, output current, transconductance, and threshold voltage resulting from the increase of temperature can be substantially suppressed.
In order to understand the barrier height of the n+-GaAs/p+-InGaP/n-GaAs camel-like structure, the calculated barrier height ΦB versus gate-source voltage VGS for different p+-InGaP
doping densities are revealed in Fig. 3.
The barrier height is increased with the increase of p+-InGaP doping density.
However, the presented too much high doping level of p+-InGaP layer cannot be fully depleted at equilibrium and under the biased condition. This induces the undesired conduction between the gate-source and gate-drain electrodes. In this work, an appropriate doping density of p+=8×10 cm-3 of InGaP layer is used.
The p+-InGaP layer is fully depleted and a large barrier height of ΦB=1.07 V is obtained at zero gate-source voltage.
The gate-drain I-V characteristics at different temperatures are shown in Fig.
4. The barrier height of 1.1 eV, extracted from semi-log I-V characteristics, of the studied n+-GaAs/p+-InGaP/n-GaAs camel-like diode is acquired. This experimental data is consistent with the calculated result. The gate-drain breakdown voltage BVGD, defined at IGD=1 mA/mm, as shown in the lower inset of Fig. 4, is as high as 52 V at room temperature. The upper inset in Fig. 4 shows the gate leakage current
IG versus different temperatures. The gate leakage currents, measured at VGD=40 V, are 0.037 and 3.5 mA/mm at the temperature of 300 and 480 K, respectively. The gate leakage current is increased with increasing the temperature. In the studied device, the high-barrier n+-GaAs/p+-InGaP/n-GaAs camel-like diode is used to prevent carriers tunneling to gate electrode. In addition, the GaAs/InGaAs heterostructure channel provides good carrier confinement. Even at high temperature, the device also reveals the relatively low leakage behaviors.
The output I-V characteristics at 300, 390, and 480 K are shown in Fig. 5.
The applied gate voltage is decreased by -0.5 V/step. The maximum applied
gate-source voltage is VGS=+1 V. All the I-V curves show good pinch-off behaviors. The threshold voltages are -1.9, -1.95, and -2.25 V at room temperature, 390, and 480 K, respectively. The maximum drain-source operation voltage is over 20 V and no significant gate leakage current is found at VGS=+1 V. It is believed that, due to the high turn-on voltage, gate leakage current is reduced at forward-biased region. Therefore, output current density and output power can be enhanced.
Figure 6 shows the drain-source off-state breakdown characteristics of the studied device measured by the drain current injection mode at room temperature, 420, and 480 K, respectively. The breakdown characteristics are considerably different among room temperature, 420, and 480 K. The VDS curve can be divided into linear, saturation, channel breakdown and gate breakdown region at room temperature. However, the channel breakdown region is not found at 420 and 480 K. When the gate breakdown is presented, the IG increases quickly with the decrease of VGS and reaches a plateau of 1 mA/mm at room temperature and 420 K. Yet, the IG increases slowly with the decrease of VGS at 480 K. We believe this is caused by the substrate leakage current at high temperature. For a fixed injection current of ID=1 mA/mm, it is known that
IG+IS=1 mA/mm. The source current IS is affected by the substrate leakage current. The substrate leakage current increases with the increase of temperature. Hence, the IS and IG are increased and decreased with the increase of temperature, respectively.
Therefore, at high temperature, the channel is more difficult to be completely depleted. In other words, a
larger VGS is needed to constrict the channel to achieve IS=0.
Figure 7 shows the three-terminal BVDS and BVDG as a function of temperature at the injection current of ID=1 mA/mm. The breakdown voltages of BVDS and BVDG are defined at the peak of VDS curve and the extraction of the point at IG=-1 mA/mm, respectively.
The BVDS and BVDG show the negative temperature coefficients. Obviously, the studied device provides high breakdown characteristics even at high temperature regime.
The dependence of the extrinsic transconductance gm on drain saturation current IDS at 300, 390, and 480 K are shown in Fig. 8. The applied voltage is fixed at VDS= 8 V. Obviously, the device show good linearity properties and high transconductance. The maximum transconductance gm,max are 147.4, 144.4, and 123.2 mS/mm at 300, 390, and 480 K, respectively. The corresponding linear IDS operation regime, defined at the drop of 10 % from the gm,max, are 225, 200, and 175 mA/mm. It is believed that, based on the good carrier confinement of the employed high-barrier gate and heterostructure channel, the leakage current is reduced and relatively linear transconductance behaviors are obtained. The transconductance gm and output conductance gds versus drain-source voltage VDS at room temperature are plotted in Fig. 9. The biased voltage is kept at VGS=0 V. At the regime of 7 V<VDS<17 V, gm and gds are large than 140 and small than 1.5 mS/mm, respectively. Thus, the voltage gain AV
(gm/gds) as high as 100 is found at this regime. The temperature-dependent characteristics of gm, gds, and AV at VDS=8 V and VGS=0 V are presented in the insertion of Fig. 9. The AV is higher
than 100 when T≦420 K. Even at high temperature of 480 K, the AV is still as high as 85. Hence, the good temperature-dependent amplification capability of the studied device is obtained.
The measured unity current-gain cut-off frequency fT and maximum oscillation frequency fmax as a function of gate-source voltage VGS are shown in Fig. 10. The microwave performances of the studied device are measured by an HP8510B network analyzer in conjunction with cascade probes at the biased conditions of VDS=8 V at room temperature. The maximum fT and maximum fmax are 15 and 28 GHz, respectively, at VGS=0 V. The dependence of fT and fmax on the drain saturation current IDS are illustrated in the inset of Fig. 11. Obviously, the fT
and fmax exhibit wide and flat VGS and IDS operation regimes.