結論

In summary, a new camel-like high-barrier gate FET with a high breakdown voltage and low leakage current has been fabricated successfully and demonstrated. In the studied 1 × 100 µm² device, due to the use of n⁺-GaAs/p⁺-InGaP/n-GaAs

camel-like-barrier gate and GaAs/InGaAs heterostructure channel structure, good carrier confinements are obtained. Therefore, the leakage current is reduced and the breakdown characteristics are improved.

Experimentally, good device performances are obtained at room temperature. In addition, the device also exhibits the high breakdown characteristics at high temperature environment and good microwave behaviors. Consequently, based on these good performances, the studied device

shows a great promise for high-breakdown, low-leakage, and high-temperature applications.

參考文獻

[1] L. W. Yin et al., IEEE Electron

Device Lett., vol. 11, pp. 561, 1990.

[2] C. L. Chen et al., IEEE Electron

Device Lett., vol. 13, pp. 335, 1992.

[3] B. T. Jeon et al., IEEE Electron

Device Lett., vol. 13, pp. 630, 1992.

[4] Y. Okamoto et al., IEE Electron

Lett., vol. 31, pp. 2216, 1995.

[5] J. B. Shealy et al., IEEE Electron

Device Lett., vol. 14, pp. 545, 1993.

[6] W. S. Lour et al., IEEE Trans.

Electron Devices, vol. 43, pp. 871,

1996.

[7] L. W. Laih et al., IEE Electron Lett., vol. 32, pp. 1418, 1996.

[8] W. L. Chang et al., Jpn. J. Appl.

Phys Lett., vol. 38, pp. L1385,

1999.

[9] J. S. Su et al., IEE Electron Lett., vol.

32, pp. 2095, 1996.

Fig. 1 The schematic cross section of the

n⁺-GaAs/p⁺-InGaP/n-GaAs camel-like gate HFET.

Fig. 2 The corresponding band diagrams

of the studied device at equilibrium (solid lines) and under applied biased (dashed lines) conditions.

≈ ≈

GaAs Buffer Layer

S. I. GaAs Sub.

300 330 360 390 420 450 480

1E-2

Gate-Source Voltage VGS (V) Barrier Height φB (V)

p⁺=1 × 10¹⁹ cm^-3 p⁺=8 × 10¹⁸ cm^-3 p⁺=6 × 10¹⁸ cm^-3

Fig. 3 The calculated barrier height Φ

B as a function of applied gate-source voltage VGS.

Fig. 4 The measured gate-drain I-V

characteristics at various temperature. The upper inset shows the gate leakage current

IG at VGD=40 V at different temperature. The lower inset shows the extended I-V characteristics at 300 K.

Drain-Source Voltage VDS (V) Drain Current ID (mA/mm)

1×100 μm²

Gate-Source Voltage VGS (V)

Gate Current IG (mA/mm) Drain-Source, Drain-Gate Voltage VDS, VDG (V)

T=300 K

Gate-Source Voltage VGS (V)

Gate Current IG (mA/mm) Drain-Source, Drain-Gate Voltage VDS, VDG (V)

T=420 K

Gate-Source Voltage VGS (V)

Gate Current IG (mA/mm) Drain-Source, Drain-Gate Voltage VDS, VDG (V)

T=480 K ID=1 mA/mm

IG

BVDS

BVDG

Fig. 5 The common source I-V

characteristics of the studied device measured at 300, 390, and 480 K, respectively.

Fig. 6 The off-state breakdown

characteristics, measured by the drain current injection mode at ID=1 mA/mm, at (a) 300, (b) 420, and (c) 480 K, respectively.

Fig. 6(c)

Fig. 6(b)

300 330 360 390 420 450 480

Temperature (K) Drain-Source, Drain-Gate Breakdown Voltage BVDS, BVDG (V)

BVDS

Drain Saturation Current I_DS (mA/mm) Transconductance gm (mS/mm)

Gate-Source Voltage VGS

1×100 μm²

Drain-Source Voltage VDS (V) Transconductance gm and Output Conductance gds (mS/mm)

gm

gds

T=300 K VGS=0 V

300 330 360 390 420 450 480

0

Temperature (K)

gds (mS/mm) Voltage Gain AV, gm (mS/mm)

VDS=8 V

Gate-Source Voltage VGS (V)

Frequency (GHz) Drain Saturation Current

IDS (mA/mm)

Fig. 7 The drain-gate and drain-source

breakdown voltage BVDG, BVDS versus temperature.

Fig. 8 The dependence of

transconductance gm on the drain saturation current IDS at room temperature, 390, and 480 K. The insertion shows the corresponding drain saturation current IDS and transconductance gm versus the gate-source voltage VGS.

Fig. 9 The measured transconductance g

m

and output conductance gds versus drain-source voltage VDS at room temperature. The insertion shows the temperature-dependent characteristics of transconductance gm, output conductance gds, and voltage gain AV.

Fig. 10 The measured unity current-gain

cut-off frequency fT and maximum oscillation frequency fmax as a function of gate-source voltage VGS. The inset shows the dependence of fT and fmax on the drain saturation current IDS.

高性能異質結構場效電晶體之研製(2/3)

The Fabrication of High-Performance Heterostructure Field-Effect Transistors (HFETs)

計劃編號：NSC 92-2215-E-006-007 執行期限：92/08/01 至 93/07/31

主持人：劉文超 教授 執行單位：國立成功大學電機系微電子工程研究所

e-mail:[email protected]

一、中文摘要

在本計劃中，我們研製一種新型的異質結 構場效電晶體，我們將砷化銦鎵/砷化鎵複合 式通道應用在異質結構場效電晶體中，並研 究其溫度效應，由於具有低的漏電流及良好 的載子侷限能力，元件的溫度效應極佳，對

一閘極尺寸為 1×100 微米的元件而言，在環

境溫度為300 與 450K 時，元件兩端閘-汲極 崩潰電壓為24.5 與 22.0V，三端開路狀態汲-源極崩潰電壓為24.4 與 18.7 V，轉導值為而 161 與 138mS/mm，而電壓增益為 268 與 263，另一方面，元件在微波頻率領域下亦顯 示出良好的操作特性。

關鍵字：複合式通道、異質結構場效電晶體、

崩潰電壓、開路狀態崩潰電壓。

二、英文摘要

The temperature-dependent characteristics of an n⁺-InGaAs/n-GaAs composite doped channel (CDC) heterostructure field-effect transistor have been studied. Due to the reduction of leakage current and good carrier confinement in the n⁺-InGaAs/n-GaAs CDC structure, the degradation of device performances with increasing the temperature is insignificant. Experimentally, for a 1×100 µm² device, the gate-drain breakdown voltage of 24.5 (22.0) V, turn-on voltage of 2.05 (1.70) V, off-state drain-source breakdown voltage of

24.4 (18.7) V, transconductance of 161 (138) mS/mm, and voltage gain of 268 (230) are obtained at 300 (450) K, respectively. In addition, the studied device also shows good microwave performances with flat and wide operation regime.

三、計劃緣由與目的

Recently, due to the rapid progress in growth technologies, many III-V compound semiconductor devices, such as heterostructure field-effect transistors (HFETs), heterojunction bipolar transistors (HBTs), and negative-differential-resistance (NDR) devices, have been successfully fabricated and investigated [1-3]. HFETs, e.g., metal-semiconductor field-effect transistor (MESFET), high electron mobility transistor (HEMT), and doped-channel field-effect transistor (DCFET), have attracted considerable attention for microwave power and digital applications due to the high current handling capability and high speed operation [4-8]. In MESFETs, the high field around the metal-semiconductor interface decreases the Schottky diode characteristics. This induces a large leakage current, low breakdown voltage, and low turn-on voltage. Therefore, output current and voltage swing are lower. On the other hand, the parallel conduction effect is found in the traditional HEMT. The conducting electrons transfer into the high bandgap layer at

higher forward bias. Due to the low electron mobility in the high bandgap layer, the device performance is degraded when forward biased.

Therefore, the DCFET, instead of traditional MESFET and HEMT, has been reported and studied. For DCFETs, the insertion of undoped high bandgap layer between the metal gate and active channel can improve the breakdown voltage and turn-on voltage. In addition, parallel conduction is avoided. Therefore, large voltage swing, high current density, and better device linearity can be achieved.

In GaAs based HFETs, it is favorable to use an InGaAs layer to replace the GaAs as a channel layer due to its higher mobility, peak electron velocity, and lower effective mass.

However, the lower InGaAs energy gap may induce impact ionization in the InGaAs layer under high electric field [9-10]. Therefore, the device performance including leakage current, output conductance, voltage gain, and drain-source breakdown voltage degrade considerably. To overcome these disadvantages, a novel device using an InGaAs/GaAs composite doped channel (CDC) structure is proposed to achieve high device performances and high-temperature operation capability.

Experimentally, low leakage current, low output conductance, high voltage gain, high breakdown voltage, and good performances at higher temperature regimes are obtained.

四、研究方法

The studied device was grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD) system on a (100)-oriented semi-insulated (SI) GaAs substrate. The epitaxial layers consisted of a 0.5 µm thick undoped GaAs buffer, a 500 Å thick undoped In0.49Ga0.51P, a 150 Å thick doped GaAs (n=5 × 10¹⁷ cm^-3), a 50 Å thick doped In0.2Ga0.8As (n⁺=4 × 10¹⁸ cm^-3), a 300 Å thick undoped In0.49Ga0.51P, and a 500 Å thick doped GaAs (n⁺=4 × 10¹⁸ cm^-3) cap layers. After the epitaxial growth, devices were processed by

conventional photo-lithographic and vacuum evaporation techniques. Mesa etching process was used to isolate the devices. The drain-source Ohmic contacts were formed on n⁺-GaAs cap layer by alloying evaporated AuGe/Ni metals at 400 ^ºC for 1 minute. The n⁺-GaAs cap layer was removed and then the gate Schottky contact was achieved by evaporating Au metal on the undoped In0.49Ga0.51P layer. Finally, layers underneath the gate feeder were completed removed by using wet etching to develop the air-bridge gate structure which includes multiple piers between gate pad and active region. The gate dimension is 1 × 100 µm². The schematic cross section of the fabricated device is depicted in Fig. 1.

五、實驗結果與討論

The corresponding band diagram of the studied device is illustrated in the Fig. 2. The undoped wide-gap In0.49Ga0.51P (~1.92 eV) material is used as Schottky gate and buffer layer. The upper In0.49Ga0.51P layer can provide good Schottky characteristics. The lower In0.49Ga0.51P layer is used to suppress the substrate leakage current through the substrate leakage path. The n⁺-In0.2Ga0.8As/n-GaAs layers form the CDC structure. The narrow InGaAs layer is used to introduce the channel quantization effect [11-13]. Thus, the effective energy-gap of InGaAs (Eg,InGaAs+ΔE) channel can be increased. The n-GaAs channel can improve the operation capability under higher electric field. Hence, the impact ionization effect can be avoided and the leakage current minimized. In addition, the large conduction band discontinuity at the In0.49Ga0.51P/

In0.2Ga0.8As and GaAs/In0.49Ga0.51P interface can provide better carrier confinement in the channel. Therefore, the device performance is improved even at higher temperature.

The measured gate-drain current-voltage (I-V) characteristics of the studied device at 300K is illustrated in Fig. 3. The reverse gate-drain breakdown voltages BVGD and

forward turn-on voltage Von as a function of temperature are revealed, respectively, in the upper and lower inset of Fig. 3. BVGD and Von

are defined at a gate current level of 0.5 mA/mm. BVGD (Von) values are 24.5 (2.05), 23.9 (1.97), 23.4 (1.93), 23.0 (1.85), 22.6 (1.79), and 22.0 (1.70) V at the temperature values of T=300, 330, 360, 390, 420, and 450 K, respectively. Due to the increase in the tunneling current and reduction in energy-gap, BVGD and Von decrease with increasing temperature. However, the device still shows high BVGD and Von at high temperatures and the rates of decrease with temperature are only on the order of 6.8×10^-4/K (BVGD) and 1.14×10^-3/K (Von). It is believed that these temperature-dependent characteristics are attributed to: (1) the properties of wide-gap InGaP gate insulator, (2) the reduced sidewall leakage current and impact ionization current, and (3) good carrier confinement in the n⁺-InGaAs/n-GaAs CDC structure. In addition, the studied device shows relatively high Von

values. This indicates the forward leakage current is reduced and the large forward gate-source voltage swing can be obtained.

Figure 4 shows the common-source I-V characteristics of the studied device measured at various temperature. All I-V curves show good pinch-off and saturation characteristics.

The maximum applied gate-source voltage is +1.5 V and no significant gate leakage current is found. This indicates that the high turn-on voltage associated with good Schottky behavior and good carrier confinement are obtained in the studied device. Figure 5 shows the gate current IG versus gate-source voltage VGS at 300 and 450 K at VDS=4.0 and 8.0 V, respectively. The gate leakage currents are less than 1.6 and 22 µA/mm at 300 and 450 K under the typical biased condition from VGS=+1.0 to -2.0 V. The undesired bell-shaped behavior, usually found in InGaAs channel FET [9-10], is not observed. As seen from the schematic band diagram in the Fig. 2, the studied device can provide good carrier

confinement and increase the effective energy-gap of the InGaAs layer to eliminate the impact ionization effect. Therefore, the leakage current can be reduced significantly at room temperature and even at higher temperature.

The off-state breakdown characteristics of the studied device measured by the drain current injection mode [14-15] at 300K are illustrated in Fig. 6. The injection currents are fixed at ID=0.5 and 1.0 mA/mm, respectively.

The off-state breakdown voltage BVDS and BVDG are defined at the peak of VDS curve and at the extraction point of IG=-1 mA/mm, respectively. Experimentally, high BVDS of 24.4 V and BVDG of 26.4 V are obtained when ID=1.0 mA/mm. In addition, it is found that the off-state breakdown characteristic is dominated by gate breakdown. When VGS>-1.4 V, the channel is conducting and VDS is small. The injection current ID (1.0 mA/mm) is nearly equal to source current IS (

≈

1.0 mA/mm) and the gate current IG

≈

0. At -2.0 V<VGS<-1.4 V, VDS and IG rise while IS decreases sharply.

However, IG+IS (=ID) is equal to 1 mA/mm. At VGS<-2.0 V, the channel is completed cut-off, all the injection current injects toward the gate electrode. Therefore, ID

≈

IG

≈

1 mA/mm and IS

≈

0. On the other hand, the same characteristics are found, and we obtain BVDS

of 22.8 V and BVDG of 24.9 V at ID=0.5 mA/mm. Figure 7 illustrates the measured BVDS and BVDG as a function of temperature at ID=1.0 mA/mm. BVDS (BVDG) values are 24.4 (26.4), 23.3 (25.3), 22.3 (24.3), 21.2 (23.4), 20.1 (22.3), and 18.7 (20.9) V at 300, 330, 360, 390, 420, and 450 K, respectively. The studied device shows a low dependence on temperature with a rate of decrease of 1.56×10^-3/K (1.39×10^-3/K) and high BVDS (BVDG) values even at 450 K. Therefore, the voltage swing of the logic circuit and the power density of the amplifiers can be improved for wide and high temperature operation.

Figure 8 represents the transconductance gm, output conductance gds, and voltage gain AV

versus drain-source voltage VDS at 300 and 450

K. Clearly, due to the reduction of leakage current, the relatively low gds and high AV are acquired. Under bias conditions of VGS=+0.5 V and VDS≥ 3.0 V, gds and gm are about 0.61 (0.60) and 160 (138) mS/mm, respectively, at 300K (450 K). The AV (gm/gds) is higher than 265 and 225 at 300 and 450 K. To further investigate the temperature dependent characteristics, AV, gm, and gds as a function of temperature at VDS=6.0 V and VGS=+0.5 V are shown in the Fig. 9. gds

values are 0.60, 0.61, 0.61, 0.61, 0.60, and 0.60 mS/mm at 300, 330, 360, 390, 420, and 450 K, respectively. It is found that gds shows low values and is insensitive to an increase in temperature. This indicates that the increase of leakage current with increasing the temperature is insignificant. In addition, the corresponding gm values are 161, 155, 151, 147, 141, and 138 mS/mm and high AV of 268, 254, 248, 241, 235, and 230 are obtained at 300, 330, 360, 390, 420, and 450 K, respectively. Therefore, good amplification performances can be achieved even at high temperatures.

The microwave characteristics of the studied device are measured by an HP8510B network analyzer in conjunction with Cascade probes. The unity current gain cut-off frequency fT and maximum oscillation frequency fmax are 15.9 and 30.5 GHz, respectively, under the bias condition of VGS=+1.0 V and VDS=6.0 V. The dependence of the frequency response on drain current are demonstrated in Fig. 10. The bias voltage is fixed at VDS=6.0 V. The slightly undulating curves in the Fig. 10 are caused by the presence of the CDC structure. In addition, the studied device shows good microwave characteristics and maintains 80% of its fT and fmax peak values over a large range of drain current between 30 to 360 mA/mm. The corresponding gate voltage swing is about of 2.5 V (-1.0 V<VGS<1.5 V). Therefore, the studied device also provides promise for high-frequency applications.

六、結論

The temperature-dependent characteristics of an n⁺-InGaAs/n-GaAs CDC heterostructure field-effect transistor have been studied and reported. The n⁺-InGaAs/n-GaAs CDC structure is used to reduce the leakage current and hold good carrier confinement in the channel. Experimentally, it is shown that the degradation of device performance with increasing temperature is insignificant. For a 1×100 μm² device, the gate-drain breakdown voltage of 24.5 (22.0) V, turn-on voltage of 2.05 (1.70) V, off-state drain-source breakdown voltage of 24.4 (18.7) V, transconductance of 161 (138) mS/mm, output conductance of 0.60 (0.60) mS/mm, and voltage gain of 268 (230) are obtained at 300 (450) K, respectively. In addition, the studied device also shows good microwave characteristics with flat and wide operation regime. Therefore, the studied device is suitable for high-temperature and microwave circuit applications.

參考文獻

[10] J. C. Liou, K. M. Lau, IEEE Trans. Electron.

Devices, vol. 35, pp. 14, 1988.

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[13] L. W. Yin, Y. Hwang, J. H. Lee, R. M. Kolbas, R. J.

Trew, and U. K. Mishra, IEEE Electron Device Lett., vol. 11, pp. 561-563, 1990.

[14] C. L. Chen, L. J. Mahoney, M. J. Manfra, F. W.

Smith, D. H. Temme, A. R. Calawa, IEEE Electron Device Lett., vol. 13, pp. 335, 1992.

[15] T. Ytterdal, B. J. Moon, T. A. Fjeldly, and M. S. Shur, IEEE Trans. Electron. Devices, vol. 42, pp. 1724, 1995.

[16] K. L. Tan, D. C. Streit, R. M. Dia, S. K. Wang, A. C.

Han, P. D. Chow, T. Q. Trinh, P. H. Liu, J. R. Velebir, and H. C. Yen, IEEE Electron Device Lett., vol. 12, pp. 213, 1991.

[17] Y. C. Wang, J. M. Kuo, F. Ren, J. R. Lothian, J. S.

Weiner, J. Lin, W. E. Mayo, and Y. K. Chen, IEEE Electron Device Lett., vol. 18, pp. 550, 1997.

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Electron. Devices, vol. 39, pp. 1849, 1992.

[19] C. Tedesco, E. Zanoni, C. Canali, S. Bigliardi, M.

Manfredi, D. C. Streit, and W. T. Anderson, IEEE Trans. Electron. Devices, vol. 40, pp. 1211, 1993.

[20] D. F. Welch, G. W. Wicks, and L. F. Eastman, Appl.

Phys. Lett., vol. 43, pp. 761, 1983.

[21] T. Enoki, K. Arai, A. Kohzen, and Y. Ishii, IEEE Trans. Electron Devices, vol. 42, pp. 1413, 1995.

[22] G. Meneghesso, A. Neviani, R. Oesterholt, M.

Matloubian, T. Liu, J. J. Brown, C. Canali, and E.

Zanoni, IEEE Trans. Electron Devices, vol. 46, pp. 2, 1999.

[23] S. R. Bahl, and J. A. D. Alamo, IEEE Trans.

Electron Devices, vol. 40, pp. 1558, 1993.

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Electron Devices, vol. 41, pp. 2268, 1994.

本計畫相關之著作、專利、學生畢業論文

[1] W. C. Liu, K. H. Yu, R. C. Liu, K. W. Lin, K. P. Lin, C. H. Yen, C. C. Cheng, and K. B. Thei,

“Investigation of temperature- dependent characteristics of an n⁺-InGaAs/n-GaAs composite doped channel (CDC) heterostructure field-effect transistor,” IEEE Trans. Electron Devices, vol. 48, pp. 2677-2683, 2001.

[2] K. H. Yu, H. M. Chuang, K. W. Lin, X. D. Liao, C. T.

Lu, and W. C. Liu, “Improved n⁺-InGaAs/n-GaAs composite-doped-channel structure for high-breakdown, low-leakage, and high-temperature applications,” 第九屆三軍官校基礎學術研討會, 高雄, pp. C1.5-11, 2002.

[3] H. M. Chuang, K. H. Yu, C. Y. Chen, X. D. Liao, K.

M. Lee, P. H. Lai, C. I. Kao, and W. C. Liu,

“Characteristics of an InGaAs/GaAs Composite Doped Channel Heterostructure Field-Effect Transistor,” EDMS’02, Taipei, pp. 133-136, 2002.

[4] 中華民國專利, 劉文超、余國輝、林坤緯, “具有複 合式摻雜通道之異質結構場效電晶體”, 專利號碼:

發明第158,646 號.

[5] 博士論文, 余國輝,“具有改良式通道之異質接面 場效電晶體之研製”, 成功大學電機系微電子工程 研究所.

[6] 碩士論文, 林冠伯,“磷化銦鎵高障壁閘極異質結 構場效電晶體晶體之研製”, 成功大學電機系.

S.I. GaAs Sub.

Drain

i-GaAs Buffer i-In0.49Ga0.51P

300-Å-i-In0.49Ga0.51P Schottky layer 50-Å-n +(4×10 18 cm -3)-In0.2Ga0.8As 150-Å-n (5×10 17 cm -3)-GaAs 500-Å-i-In0.49Ga0.51P 5000-Å-i-GaAs-Buffer

EF

300 330 360 390 420 450 1.6

300 330 360 390 420 450 21

Turn-on Voltage Von (V) Breakdown Voltage BVGD (V)

Gate-Drain Voltage VGD (V) Temperature (K)

Temperature (K) Gate Current IG (mA/mm)

T

Drain-Source Voltage VDS (V)

Drain Current ID (mA/mm) ^VGS= _{+1.5 V} Fig. 1 The schematic cross section of the studied

device.

Fig. 2.The band diagram of the studied device.

Fig. 3 The measured gate-drain I-V characteristic of the studied device at 300K. The upper and lower insets show BVGD and Von versus temperature, respectively.

Fig. 4 The common source I-V characteristics at different temperature.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

Gate-Source Voltage VGS (V) Gate Current IG (μA/mm) ^{300 K}

Gate-Source Voltage VGS (V)

Drain-Source Voltage VDS (V) and Drain-Gate Voltage VDG (V) Gate current IG and Source Current IS (mA/mm)

VDS

300 330 360 390 420 450

18

Off-State Drain-Source, Drain-Gate Breakdown Voltage BVDS, BVDG (V)

Temperature (K)

1×100 μm²

Drain-Source Voltage V_DS (V) Transconductance gm and Output Conductance gds (mS/mm)

V_GS=+0.5 V

Fig. 5 The gate current IG versus gate-source voltage VGS at 300 and 450 K at VDS=4.0 and 8.0 V, respectively.

Fig. 8 The measured transconductance gm, output conductance gds, and voltage gain AV versus drain-source voltage VDS at 300 and 450 K, respectively.

Fig. 6 The off-state breakdown characteristics measured by the drain current injection mode at

Fig. 6 The off-state breakdown characteristics measured by the drain current injection mode at

在文檔中 高性能異質結構場效電晶體之研製(3/3) (頁 8-29)