待續的工作

hvic 的可靠度驗證過程有一些作法 , 或推得數據並不完善 . 在此 提 3 個項次提供有志於此研究者參考 .

(1) 封裝形態會影響 ESD MM 的承受力 , 它的形成被比較為電場集 中的速度問題 . 對接點電阻 , 路徑 , 電場均度需要有假設的物理 模式 , 並進行實驗驗證才算完整 .

(2)積體電路的壽命推估驗證 , 以往的作法都採用溫度 , 電壓兩個加 速因子 . 本驗證使用電壓單一因子 , 其實驗結論供定性一定是對 的 , 其精準度需有更多的驗證作比較 .

(3) 本論文的試驗雖找到 SLESD 防制的方法 , 但是晶片 , PCB, 次系統對 ESD 承受力的分工並沒有被清楚的討論 . 希望會有跨 chip level , board level 及 system level 的論述或組織能深入的討論 , 而獲得一致的作法

參考文獻 參考文獻 參考文獻 參考文獻

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