本研究對於 PEC 氧化法對於元件的影響提出新的觀察，然而在物理上並沒有 驗證造成此影響的理由，一般對於氧化層與元件接面的研究常見的作法為電容電 壓量測(C-V measurement)，而對於沉積式氧化層/AlGaN/GaN 結構，已有多組研究 成果[8-10, 12, 40-42]，而對於 PEC 氧化層/n-GaN 結構，除了本實驗室早期的研究 成果[14]之外，也有其他研究者對這類結構進行研究[43, 44]，然而對於 PEC 氧化 層/AlGaN/GaN 結構接面，並沒有相關研究，如何對於沉積式氧化層/PEC 氧化層 /AlGaN/GaN 的複雜結構進行詳細的探討將是一大挑戰。
對於增強型電晶體方面，雖然本研究提出了有效方法達成此目的，然而元件 特性並非十分理想，漏電流相對較多，除了增加 ALD 氧化層厚度外，是否有其他 手段在不會降低轉導特性下，降低元件漏電流，是本研究短期的目標；另外，高 頻、大功率元件是本實驗過去的目標之一，以此製程方法，製作增強型高頻元件 或許可超越過去的成就。最後，使用矽(Si)作為基板的 AlGaN/GaN 磊晶晶片(GaN on Si)，是 GaN 製程與 Si 製程整合的方向，以 GaN on Si 樣品，製作 AlGaN/GaN HEMT 也是本研究的下一個目標。
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