未來展望

實驗結果證實電晶體沉積具有應力之 CESL 層結合矽鍺通道結構確實能 提升元件之效能，而本論文所提及之模擬方法與預測結果亦能與實驗結果相 符合。然而，通常電晶體元件製程使用之結構佈局圖，因考慮到批次生產之 特性，故將元件設計為多閘極之結構，而本研究於模擬分析時則只考慮單一 元件之設計，此種三維結構仍無法完整真實呈現實際元件製程之幾何結構。

因此，三維模型應更一步地考慮主要元件周圍建構虛擬電晶體元件結構，用 以討論相鄰之元件對於該元件通道應力的影響，致使獲得更精確的通道內應 力分佈，進而與真實電晶體特性相互匹配。

89

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