降低功率消耗降低功率消耗降低功率消耗降低功率消耗
本篇設計的摺疊架構中，在每回合的最後一個時間點難免會有一些運算單元 是不必運算的，但架構中沒有關閉運算器計算的機制，導致功率的消耗，故可以 在硬體設計中加入運算器自動調整計算開啟或關閉的切換開關，以節省電力的浪 費。
非整除摺疊架構非整除摺疊架構非整除摺疊架構非整除摺疊架構
在3.3.2 節中有簡單地介紹非整除摺疊架構的排程矩陣的排法，這只是其中
一種作法，雖然可以很簡單地去實現非整除摺疊架構，但在最後一回合中會出現 幾個乘加器是不做工的，未能加以利用造成浪費，此時，醞釀另一非整除摺疊排 程矩陣的構想，將摺疊工作回合數(即f回合)擴展成K taps數與r MACs數的最 小公倍數，便能解決上述問題，未來能繼續朝此方向來改善並研究更適合的排程 方法。
發展具備使用者介面之發展具備使用者介面之發展具備使用者介面之發展具備使用者介面之 IP 合合合合成器成器成器成器
本篇論文提出的新摺疊演算法架構具有相當的規則性，可以發展一套參數輸 入介面即(taps數 , MACs數 , x輸入位元長度 , h係數位元長度 , 規格要求精確 度) = ( K , r , m , b , L )，讓軟體自動產生HDL code來實現符合規格要求硬體，
增加摺疊演算法面積大小與功率消耗選擇的彈性，以期在規格允許範圍內及最短 時間內能有最佳效能表現。
參考文獻 參考文獻 參考文獻 參考文獻
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