第六章 結論與未來工作
6.2 未來工作
由實驗結果來看，在本系統實作 SURF 演算法之效能有待改善，因此提出下 列四項做為未來的改善方向：
1. 分析各項運算的時間，使 DSP 記憶體及 EMIF 介面的使用達到最佳化。
2. 本 系 統 最 初 的 電 路 規 劃 主 要 希 望 能 運 用 在 機 器 人 進 行 嵌 入 式 影 像 處 理 ， 故 FPGA 選 用 Altera 公 司 低 消 耗 功 率 及 高 性 價 比 的 Cyclone II 系 列 ， 型 號 為 EP2C35F672C6。但電路設計時有先預留 FPGA 的升級空間，可以選擇同系
列 中 最 高 等 級 並 且 封 裝 同 樣 是 672-Pin FineLine BGA 的 EP2C70F672C6 。 表6-1 是兩者的內部資源 比較，由表中可看出 2C70 的邏輯單元是 目前的 2 倍多，記憶體位元大約是2.38 倍，嵌入式乘法器的數量大約是 4.28 倍。
3. 以目前實作的 SURF 演算法來看，尋找興趣點的程序具有規律性，但興趣點 的產生與畫面有關而沒有一定的規則。因此，可以進一步將 Fast-Hessian 興 趣 點 偵 測器以FPGA 來實現，當找到興趣點之後先存入雙時脈 FIFO，再由 DSP 讀出後進行 SURF 描述子的計算，如此可以 讓 DSP 與 FPGA 採用類似 Pipeline 方式同步進行運算以提高計算效能。除此之外，由於 CMOS 影像感 測器是逐列地輸出影像資料，而計算 SURF 描述子最大需要以興趣點為中心 計 算20s X 20s 方形區域內的 Haar 小波響應，此時 CMOS 影像感測器的輸 出卻 尚 未達 到可計算 Haar 小波響應的列數，故 FPGA 無法在偵測到興趣點 後 立即 計算 描述 子 。 因此 將 描 述 子 的計 算 放 在DSP ，而 DSP 與 FPGA 之間 儲存興趣點的FIFO 正好可當做緩衝區。
4. 在電路設計方面，考慮將 DSP 與 FPGA 模組分成兩個獨立的電路板，兩者之 間以Piggyback 的方式連接。如此不但可以進一步縮小尺寸，而且可以個別 對FPGA 或 DSP 進行更新與升級，甚至也能夠改變組合的方式，例如：使用 近年發展快速的ARM 處理器等。
最後，此系統並沒有限定只能實現 SURF 演算法，初期只是先以 SURF 來評 估並驗證系統功能。 因此往後還需多做不同的演算法實作，藉以收集更多 的實驗 數據，或者另外研究演算法實現於本系統 的評估方式。如此一來，就可以有準則 來判斷此系統是否適用於新的演算法。
表6-1 FPGA EP2C35F672 與 EP2C70F672 內部資源比較 EP2C35F672 EP2C70F672
LEs 33,216 68,416
M4K RAM blocks 105 250
Total RAM bits 483,840 1,152,000
Embedded Multipliers 35 150
PLLs 4 4
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