因著技術不斷的進步，奈米製程已是現今半導體的趨勢，而近年來，其他學 者提出應變矽技術以提高元件的載子遷移率，進而提升元件的驅動電流，當矽晶 格受到應力產生應變，可將傳輸載子之有效質量縮小，遷移率增加及越容易達到 飽和速度。若使用應變矽技術作為載子傳輸通道，電子與電洞的載子遷移率有可 能皆增加，達到增加元件速度與驅動電流的目標。而由於矽與鍺晶格匹配不均，
所以鍺元素須以些微方式增加在製程中，使應變的效果保持在於基板內，以保持 低的差排密度，藉由磊晶矽緩衝層的沉積，可有效地減少矽基底與矽鍺通道差排 所帶來的不利影響。
在本研究中，第一、二、三階段的實驗，都採用 p 型應變矽電晶體於不同矽 覆蓋層(Si-cap)厚度下(24Å 、39Å )做電特性研究，其應變強度與通道介面的連 結是習習相關的。由於沉基一層適當厚度的矽覆蓋層，可以避免鍺原子擴散至閘 極介電層，使得通道的 Interface state 可有效降低，ΔIon可明顯的提高。另外，接 面漏電流的影響大小與元件的通道長度和溫度也有相關[25-28]。圖 5.1 為 p 型元 件接面漏電流與溫度的關係圖，元件尺寸為10μm/10μm，圖 5.2 為 p 型元件遷移 率與溫度的關係圖，元件尺寸為10μm/10μm。圖 5.3 為 p 型元件接面漏電流與溫 度的關係圖，元件尺寸為10μm/0.08μm，圖 5.4 為 p 型元件遷移率與溫度的關係 圖，元件尺寸為10μm/0.08μm。
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圖 5.1 p 型元件邊緣接面漏電流與溫度的關係圖，元件尺寸為 10μm/10μm
圖 5.2 p 型元件有效遷移率與溫度，元件尺寸為 10μm/10μm
由圖 5.1 和圖 5.2 可發現，溫度從 25℃至 125℃時，Non-strained 元件的接面 漏電流為最小，遷移率也最小。照理來說，接面漏電流越小，遷移率會越大，但 是 Non-strained 與此現象相反，目前推測，是因為與通道長度大小和汲極端接面 處的缺陷有關。在圖 5.2 可知，Si-cap 24Å 的厚度最適合當作元件的矽覆蓋層，
另外，透過圖 5.1 和圖 5.2 可發現，當溫度越來越高時，接面漏電流會越大，遷 移率會越小，其原因與晶格擾動有關。
圖 5.3 p 型元件邊緣接面漏電流與溫度的關係圖，元件尺寸為 10μm/0.08μm
圖 5.4 p 型元件遷移率與溫度，元件尺寸為 10μm/0.08μm
由圖 5.3 和圖 5.4 可發現，溫度從 25℃至 37℃時，Non-strained 元件的接面 漏電流為最大，但是當溫度從 37℃至 112℃，Non-strained 的接面漏電流逐漸變 成最小，當 112℃至 125℃時，Non-strained 的接面漏電流又變回最大，而以上的 現象，與溫度加熱和元件的長度有很大的關連性。另外，由圖 5.2 和圖 5.4 可發 現，在圖 5.4 的元件尺寸為 10μm/0.08μm，不論是不同 Si-cap 和 Non-strained 元 件的遷移率都比圖 5.2 的元件尺寸為 10μm/10μm 來的小，其主要是因為本研究 的元件是採用 PMOS 元件，元件的尺寸為 W/L=10μm/10μm，並搭配 CESL 壓縮 應變，所以在長通道之下(W/L=10μm/10μm)，遷移率會比較高，其與有效質量有 相關性影響。
最後，應變矽雖然已經漸漸地且廣泛地被研究，可提高電子遷移率和增加驅 動電流，但在可靠度方面卻較少人探討到。諸如如何降低熱載子注入(Hot carrier injection, HCI)效應，以及改善載子注入在奈米等級製程元件中，亦是非常重要的 探討議題[29-30]，此等議題可作後續的研究。
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明新科技大學 101 年度 研究計畫執行成果自評表
論文發表: 計畫期間 01/2012~ 09/2012
1. Hsin-Chia Yang, Jui-Ming Tsai, Jhe-Chuan Yeh, Cheng-Huang Tsao, Sungching Chi, Tsing-Yung Chang, Mu-Chun Wang, “Promising Low Noise Amplifiers Using 90nm CMOSFET Devices,” IEEE/ 8th International Conference on Wireless Communications, Network and Mobile Computing (WiCOM 2012), Sept. 2012, Shanghai, China.
2. Piyas Samanta*, Heng-Sheng Huang, Shuang-Yuan Chen, Tsung-Jian Tzeng, and Mu-Chun Wang, “Interface trap generation and recovery mechanisms during and after positive bias stress in metal-oxide-semiconductor structures,”
Applied Physics Letters (APL), vol. 100, pp. 203503-1~4, May 14, 2012. (SCI IF 2010: 3.841)
3. 王木俊*、張敬宗、吳國維、楊信佳、陳肇業,“0.18 微米製程 2.4GHz 高輸出增益與低雜訊指數疊接式低雜
訊放大器整合於 RFID 晶片”2012 電子工程技術研討會, 高雄, 台灣, 6 月 1 日 2012.
4. 王木俊*、彭思豪、吳國維、楊信佳、陳肇業,“0.18 微米製程 5.2/5.8GHz 高增益與絕佳隔離之疊接式低雜
訊放大器應用於射頻鑑別系統”2012 電子工程技術研討會, 高雄, 台灣, 6 月 1 日 2012. (口頭優秀論文獎) 5. Mu-Chun Wang*, Tien-Tsorng Shih, Bao-Yi Lin, Hsin-Chia Yang, Yaw-Dong Wu, Chuan-Hsi Liu, “A Study of
Characteristics of Halogen-Free Prevented Solder Materials,” IEEE/ 2012 International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), B-11, Aug., 2012, Guilin, China.
6. Szu-Hung Chen, Wen-Shiang Liao, Hsin-Chia Yang, Shea-Jue Wang, Yue-Gie Liaw, Hao Wang, Haoshuang Gu and Mu-Chun Wang*, “High-Performance III-V MOSFET with Nano-stacked High-k Gate Dielectric and 3D Fin-shaped Structure,” Nanoscale Research Letters (NRL), vol. 7, iss.1, p.431, Aug. 2012.(SCI IF 2011: 2.73 ) 7. Mu-Chun Wang*, Guo-Wei Wu, Wen-Shiang Liao, Hsin-Chia Yang, Tsao-Yeh Chen, “Junction Potential of
Uniaxial CESL Strained Nano-regime pMOSFETs on <100> Silicon Wafer,” 10th Conference on Microelectronics Technology and Applications at National KaoHsiung Marine University, Semiconductor Device Group, paper number A1., May, 2012, Taiwan.
8. Mu-Chun Wang*, Yi-Hong Li, Wen-Shiang Liao, Chung-Kuan Du, Hsin-Chia Yang, Tsao-Yeh Chen, “Junction Potential of Strained Nano-regime nMOSFETs on <100> Silicon Wafer with Refilled Si S/D and Compressive CESL Processes,” 10th Conference on Microelectronics Technology and Applications at National KaoHsiung Marine University, Semiconductor Material Group, paper number B3., May, 2012, Taiwan.
9. Tsao-Yeh Chen, Chung-Kuan Du, Wen-Shiang Liao, Jing-Zong Jhang, Hsin-Chia Yang, Tsao-Yeh Chen, Ming-Feng Lu, Mu-Chun Wang*, “A Study of Junction Potential of Refilled Si S/D Process for Nano-regime MOSFETs on <100> Silicon Wafer,” 10th Conference on Microelectronics Technology and Applications at National KaoHsiung Marine University, Semiconductor Device Group, paper number A3., May, 2012, Taiwan.
10. Mu-Chun Wang*, Jing-Zong Jhang, Wen-Shiang Liao, Hsin-Chia Yang, Tsao-Yeh Chen, Ming-Feng Lu,
“Nano-scale Compressive Strained CESL Impacting Junction Potential of pMOSFETs on <100> Si Wafer,” 10th Conference on Microelectronics Technology and Applications at National KaoHsiung Marine University, Semiconductor Device Group, paper number A10., May, 2012, Taiwan.
11. Mu-Chun Wang*, Ssu-Hao Peng, Hsin-Chia Yang, Tsao-Yeh Chen, “2.4GHz High Gain and High Isolation of Cascade Low Noise Amplifier in RFID,” 10th Conference on Microelectronics Technology and Applications at National KaoHsiung Marine University, System Design Group, paper number D16., May, 2012, Taiwan.
12. Mu-Chun Wang*, Ssu-Hao Peng, Wen-Shiang Liao, Hsin-Chia Yang, Tsao-Yeh Chen, Ming-Feng Lu, “Junction Potential vs. Channel Lengths of Compressive/ Tensile Strained CESL Nano-regime nMOSFETs on <100> Silicon Wafer,” 10th Conference on Microelectronics Technology and Applications at National KaoHsiung Marine
University, Semiconductor Material Group, paper number B14., May, 2012, Taiwan.
13. Hsin-Chia Yang, Wei-Yen Peng, Wen-Shiang Liao, Ssu Hao Peng, Tsao-Yeh Chen, Mu-Chun Wang*, “Variation of Junction Potential of Nano-regime nMOSFET with Tensile Strained CESL Process on <100> Si Wafer,” 10th Conference on Microelectronics Technology and Applications at National KaoHsiung Marine University, Semiconductor Material Group, paper number B15., May, 2012, Taiwan.
14. Mu-Chun Wang*, Cheng-Kuang Chuan, Wen-Shiang Liao, Hsin-Chia Yang, Tsao-Yeh Chen, “Nano-Scale CESL Strain and Refilled S/D SiGe Process Influencing Junction Performance on <110> Silicon Substrate,” 10th Conference on Microelectronics Technology and Applications at National KaoHsiung Marine University, Semiconductor Material Group, paper number B21., May, 2012, Taiwan.
15. H. W. Hsu, H. W. Chen, H. S. Huang, C. P. Cheng, K. C. Lin, S. Y. Chen, M. C. Wang*, C. H. Liu*, “Time Dependent Dielectric Breakdown (TDDB) Characteristics of Metal-Oxide- Semiconductor Capacitors with HfLaO and HfZrLaO Ultra-Thin Gate Dielectrics,” Solid State Electronics (SSE), vol. 55, pp.2-6, Nov., 2012. (SCI IF2010:
1.438 ) (*: corresponding author)
16. Chuan-Hsi Liu*, Hung-Wen Hsu, Hung-Wen Chen, Pi-Chun Juan, Mu-Chun Wang, Chin-Po Cheng, Heng-Sheng Huang, “Reliability Characteristics of Metal-Oxide-Semiconductor Capacitors with 0.72 nm Equivalent-Oxide-Thickness LaO/HfO2 Stacked Gate Dielectrics,” Microelectronic Engineering (MEE), vol. 89, pp.15-18, Jan.. 2012. (SCI IF 2010: 1.575).
明新科技大學 101 年度校內專題研究計畫 運用於教學成果記錄表
製作教材與 教具
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