5.1 結論
本論文中，我們實現了遲滯控制升壓電源轉換電路，並著重於遲滯比較器的 設計，用以降低電源轉換電路的輸出漣波，觀察不同負載R 對輸出電壓L Vout的影 響。
我們使用 TSMC T18 (T18, TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8 V&3.3 V) 製程，配合 HSPICE 軟體執行佈局前與佈局後 模擬，經由反覆的驗證和修改電路，完成遲滯控制升壓電源轉換電路晶片設計，
而實現後的晶片面積為0.723×0.723mm2。佈局後模擬結果顯示，附掛不同負載並 使用遲滯比較器的升壓電源轉換電路能成功將1.8V的供應電源轉換至約2.5V的 電壓輸出，並且抑制輸出漣波在50mV至55mV，而電源轉換效率為 81.95 %，電 路的功率消耗為14.4614mW。
5.2 未來研究方向
我們認為遲滯比較器能有效降低輸出漣波，來達到供應電源經轉換後輸出電 壓的準確性，在未來希望能設計出更準確的遲滯比較器，並使用較先進的製程加 快電晶體反應時間，亦能減少實現後的晶片面積。外掛元件中使用到的二極體，
相對於主動元件來說電阻較高，導致電源轉換效率不高，未來希望能找到合適的 主動元件應用。外掛電容的使用，希望能縮小電容值同時實現成晶片，以減少外 接電路線路過長的問題。至於輸入訊號的部份可使用現有的電路產生不重疊的時 脈訊號。
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