附錄 A CAN 實驗操作步驟

在附錄A 中所引用的資料來源是 Philips 公司 Stand-alone CAN controller SJA1000 的 Data Sheet 與 Application Note [8][24]。

‹ CAN 節點架構圖

SJA1000 是 Standard-alone CAN controller 無法獨立運作，必須以 Host Controller 設定 SJA1000，並透過 Transceiver 上傳訊息到 CAN BUS 上。

其架構如圖一所示。在SJA1000 中訊息的傳送是由 Host Controller 透 過Interface Management Logic 寫入 Transmit Buffer 再由 CAN Core Block 傳送到 Transceiver 到 CAN BUS 上。訊息的接收則是 Transceiver 接收到訊息，透過CAN Core Block 到 Acceptance Filter 判斷是否要接 收訊息，若訊息通過Acceptance Filter 傳到 Receive FIFO，再透過 Interface Management Logic 傳到 Host Controller。

圖A.1 CAN 節點架構圖 [8]

在本實驗設計中，節點是由Host Controller 8051、Standard-alone CAN Controller SJA1000 與 Transceiver PCA82C251 構成，其接線圖如圖 A.2 所 示。

圖A.2 CAN 節點接線圖 [8]

‹ CAN 資料欄框

在CAN BUS 線上傳送資料的欄框，如圖 A.3 所示包含:欄框起始(Start of Frame)、仲裁區(Identify Field)、控制區(Control Field)、資料區(Data Field)、循環多餘碼區(CRC Field)、確認區(Acknowledgment Field)與欄 框終止(End of Frame)。

圖A.3 CAN 資料欄框

‹ Acceptance Filter

資料欄框的接收與否是透過Acceptance Filter 作判斷。Acceptance Filter 是由兩個暫存器:ACR 與 AMR 所控制。ACR 是 Acceptance Code register 設定要接收的訊息Identifier。AMR 是 Acceptance Mask register 設定 Acceptance Filter 的遮罩。若 AMR 的位元設定為 1，則 ACR 的對應位元不 論事0 或 1 都可通過 Acceptance Filter，反之若 AMR 的位元設定為 0，則 只有與ACR 對應位元相同者，可通過 Acceptance Filter。Example 1 是在 PeliCAN Mode、Single Filter Mode 下的設定，其設定如圖 A.4 所示。

圖A.4 PeliCAN Mode、Single Filter Mode 下 Acceptance Filter 的設定 [8]

Example: Receive ID: 0000 0000 001 AcceptCode0Reg = 0x00;

AcceptCode1Reg = 0x2F;

AcceptCode2Reg = 0xFF;

AcceptCode3Reg = 0xFF;

AcceptMask0Reg = 0x00; //only receive 0x00 0x2F AcceptMask1Reg = 0x1F; //RTR don’t care

AcceptMask2Reg = 0xFF;

AcceptMask3Reg = 0xFF;

Example: all pass filter

AcceptCode0Reg = don’t care AcceptCode1Reg = don’t care AcceptCode2Reg = don’t care AcceptCode3Reg = don’t care AcceptMask0Reg = 0xFF;

AcceptMask1Reg = 0xFF; //RTR don’t care AcceptMask2Reg = 0xFF;

AcceptMask3Reg = 0xFF;

‹ Arbitration

若有多個資料欄框同時在CAN BUS 上傳送，則決定傳送的訊息是 Arbitration Field 較小者優先權越高。其操作如圖 A.5 所示。

圖A.5 位準仲裁圖

‹ SJA1000 的操作

„ SJA1000 有五種設定模式:Mode0(Reset Mode)、Mode1(Listen Only Mode)、Mode2(Self Test Mode)、Mode3(Acceptance Filter Mode ) 與Mode4(Sleep Mode)，五種操作模式的功能如表 A.1 所示，選擇 何種操作模式是由Mode control register 控制。

Example:

ModeControlReg = 0x01 ; //Enter reset mode

ModeControlReg = 0x08; // Enter Acceptance Filter Mode Select Single Filter

表A.1 bit interpretation of Mode register [24]

„ 在程式運作過程中如果要知道 SJA1000 的狀態，可由 Status register 得知，Status register 的代表意思如表 A.2 所示。如要得知 SJA1000 的狀況，可油下列的Example 來取得各種 Status 的狀態。

Example:

if (StatusReg&0x01){} //SR0:receiver buffer status, 1:full, 0:empty if (StatusReg&0x04){} // SR2:transfer buffer status, 1:full, 0:empty

表A.2 bit interpretation of Status register [24]

„ 要使 SJA1000 運作必須透過 Command register 來操作，Command register 有五種操作法:CMR0(Transmission Request)、CMR1(Abort Transmission)、CMR2(Release Receive Buffer)、CMR3(Clear Data Overrun)、CMR4(Self Reception Request)。Command register 五種 操作模式所代表的功能如表A.3 所示。

Example:

/*a message want to transmit, set the Transmission Request*/

CommandReg = 0x01; //CMR0:Transmission Request //1:a message will be transmitted

/*after receive a message, release Receive Buffer*/

CommandReg = 0x04; //CMR2:Release Receive Buffer // 1:released, 0:no action

表A.3 bit interpretation of Command register [24]

„ Clock divider register 用來選擇 SJA1000 所使用的 CAN 模式

(1:PeliCAN, 0:BasicCAN)，選擇內部或外部震盪器，以及Clock out frequency。其功能如表A.4 所示。

Example:

ClockDivideReg = 0xC8 ; //Peli CAN mode, Rx0 is active Rx1 ground,

//External CLKOUT off //Clock out frequency = fosc/2

表A.4 bit interpretation of Clock divider register [24]

„ The output control register 是利用軟體來設定不同的 output driver。

其功能如表A.5 所示。

Example:

OutControlReg = 0x1A ; //normal output mode //Tx0 Push-pull Tx1 Float

表A.5 bit interpretation of output control register [24]

‹ SJA1000 bit time

要設定SJA1000 的 bit time 要設定的暫存器: bus timing register 0(BTR0) 與bus timing register 1(BTR1)。其計算方式如圖 A.6 所示。

圖A.6 bit time 的計算方法 [24]

XTAL

Example 1 : 500kbits/sec, BTR0=0x01, BTR1=0x18, f 12MHz

1 1

t (sec)

f 12 10

t 2 t (32 BRP.5+16 BRP.4+8 BRP.3+4 BRP.2+2 BRP.1+BRP.0+1) 2 1 (32 0+16 0+8 0+4 0+2 0+1+1)

t t (8 TSEG1.3+4 TSEG1.2+2 TSEG1.1+TSEG1.0+1) 1 (8 1+4 0+2 0+0+1)

6 10

9 (sec) 6 10

t t (4 TSEG2.2+2 TSEG2.1+TSEG2.0+1) 1 (4 0+2 0+1+1)

SYNCSEG TSEG1 TSEG2

6 transmitting rate 1

2 10

‹ 初始化 SJA1000 的設定流程

The host controller has to configure the following registers of the control segment of the SJA1000 in reset mode:

„ Mode Register (in PeliCAN mode only), selecting the following modes of operation for this application

– Acceptance Filter mode – Self Test mode

– Listen Only mode

„ Clock Divider Register, defining

– if the BasicCAN or the PeliCAN mode is used – if the CLKOUT pin is enabled

– if the CAN input comparator is bypassed

– if the TX1 output is used as a dedicated receive interrupt output

„ Acceptance Code and Acceptance Mask Registers

– defining the acceptance code for messages to be received

– defining the acceptance mask for relevant bits of the message to be compared with corresponding bitsof the acceptance code

„ Bus Timing Registers, see also [6]

– defining the bit-rate on the bus

– defining the sample point in a bit period (bit sample point) – defining the number of samples taken in a bit period

„ Output Control Register

– defining the used output mode of the CAN bus output pins TX0 and TX1 Normal Output Mode, Clock Output Mode, Bi-Phase Output Mode or Test Output Mode

– defining the output pin configuration for TX0 and TX1 Float, Pull-down, Pull-up or Push/Pull and polarity

Example: CAN initial 程式碼

ModeControlReg = 0x01 ; // Enter reset mode

ClockDivideReg = 0xC8 ; //Peli CAN mode, Rx0 is active Rx1 ground //External CLKOUT off

//ACR|AMR

AcceptCode0Reg = 0xFF;

AcceptCode1Reg = 0x00;

AcceptCode2Reg = 0xFF;

AcceptCode3Reg = 0xFF;

AcceptMask0Reg = 0x00;

AcceptMask1Reg = 0x1F;

AcceptMask2Reg = 0xFF;

AcceptMask3Reg = 0xFF;

// External Oscillator 12MHz, bit-Rate 250k bps BusTiming0Reg = 0x00 ;

„ The host controller has to check the “Transmit Buffer Status” flag (TBS) of the Status Register, if a new message can be place replaced into The

Transmit Buffer.

„ Write TxFrameInfo, TxIddetify, TxBuffer to the Transmit Buffer.

„ Set Transmit Request.

„ Wait Transmit Complete.

Example: Transmit 程式碼

void CAN_TRAN(Byte ID, Byte CANData) {

Byte Tmp1,Tmp2;

if( StatusReg & 0x04) // Transmit Buffer Status released {

Tmp1=ID>>3; // ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 Tmp2=ID<<5; // ID.20 ID.19 ID.18 X X X X X

CommandReg = 0x01; //CMR0:Transmission Request 1:a //message will be transmitted

while ( !(StatusReg & 0x08) ); //wait complete transimt }

}

‹ Receive Message 的設定流程

„ The host controller has to check the “Receive Buffer Status” flag (RBS) of the Status Register. Is The Receive Buffer is full?

„ Receive data from The Receive Buffer.

„ After take the receive data, release The Receive Buffer.

Example: Receive 程式碼 void CAN_RECE(void) {

Byte Tmp1,Tmp2;

if(StatusReg&0x01) //SR0:receiver buffer status, 1:full, 0:empty {

Tmp1=RxIdentify1<<3;

Tmp2=RxIdentify2>>5;

CANID=Tmp1|Tmp2;

UartByteHex(CANID); //output receive CANID

CommandReg = 0x04; //CMR2:Release Receive Buffer, 1:released, 0:no action

} }