第三章 資料序列器
4.4 雷射二極體驅動電路量測
Pattern DUT generator
50Ω
HP 86100B oscilloscope Pattern DUT
generator
50Ω
HP 86100B oscilloscope
圖4-7 儀器架設
這個雷射二極體驅動器主要設計在提供 40~100mA的調變電流,以及一個 1~60mA的切換電流,量測的方式分為電氣量測及光學量測,輸入信號由一個信 號產生器產生231-1 的隨機二元資料送入電路中,一端以AC couple的方式接到示 波器中以電氣方式量測,另一端以50Ω匹配之後接到一個等效內阻為 50Ω的雷射 二極體(NEL, NLK5B5E2FA)再經由光纖傳送到示波器中,圖 4-8 為以電氣方式量 測的輸出眼圖,圖4-8(a)為調變電流為 40mA,而圖 4-8(b)為調變電流為 100mA 時的輸出,都有符合SNET OC-192 的眼圖遮罩規格,圖 4-9 所示為輸出眼圖符合 10Gbps Ethernet Network的眼圖遮罩規格,輸入的信號主要是來自於儀器 231-1 PRBS generator 所產生的PECL 的隨機信號,在Imod=100mA時 Tr/Tf=47ps,在 1mod=40mA時Tr/Tf=46ps,決定性抖動約為 22.2psp-p,隨機抖動為 2.86psrms,圖 4-10 為雷射二極體驅動電路的晶片照相圖,所使用的製程為 0.35µm SiGe BiCMOS process,總面積大約為 1430×940µm2,總共的消耗功率為1.08W,整個 效能如表4-1 所示。
(a) (b)
圖4-8 LD driver量測眼圖(SONET OC192) (a)Imod=40mA, (b)Imod=100mA
(a) (b)
圖4-9 LD driver量測眼圖(10GbEthernet) (a)Imod=40mA, (b)Imod=100mA
圖4-10 雷射二極體驅動電路晶片照相圖
Driver Summary
Supply Voltage 3.3 V
Total Power 1.08W
Bias Current 1~60mA
Modulation Current 40~100mA
Input Pattern 10 Gbps 231-1 PRBS Generator
Rise/Fall Time 47ps
Deterministic Jitter 22.2psp-p/2.86psrms
Chip Size 1430x940 µm2
Process 0.35um SiGe BiCMOS
表4-1 雷射二極體驅動電路效能
第五章
結論
5.1 結論
本論文研究內容主要著重於同步光纖網路 SONET OC-192 系統中的發射器 電路,內容包括一個 10Gbps 的資料序列器,以及一個 10Gbps 的雷射二極體驅 動器,晶片是以0.35µm SiGe BiCMOS 製程設計而成,我的研究成果分述如下。
首先是提出一個在發射器前端的資料序列器的架構,可以將 16 筆並列式的 625Mbps的資料轉成一筆串列式的 10Gbps的二元資料,多工器為樹狀架構,資 料在傳遞過程被錯排成不同的相位,可以因此而減少一些功率的消耗,並且使用 時脈倍頻器來產生多種頻率及相位的時脈信號當作多工器的選擇信號,時脈倍頻 器的迴路頻寬可以使輸出的雜訊低於OC-192 的抖動規格,並且能保證迴路處於 一 個 穩 定 的 狀 態 , 電 壓 控 制 振 盪 器 輸 出 正 交 相 位 , 輸 出 頻 率 範 圍 大 約 為 9.89GHz~11.36GHz,可以使這個時脈倍頻器可以應用在SONET OC-192 包括有 誤碼更正時的傳輸率、10Gbps Ethernet、及Optical Transport Network,為了量測
時的方便性,我們另外內建了一個隨機碼產生器,可以產生 16 筆並列式的
625Mb/s 的 資 料 , 送 給 多 工 器 來 驗 證 多 工 器 的 效 能 , 整 個 晶 片 面 積 為 2240×2260µm2,電源電壓3.3V之下,消耗的功率為 594.66mW,模擬的資料序列 器輸出結果為1.9psp-p。
第二部分為實現一個操作在 10Gbps的雷射二極體驅動電路,可以將資料序 列器輸出的電壓信號經由驅動電路轉換成電流信號,雷射二極體的偏壓電流為 1~60mA,調變電流為 40~100mA,內部電路包括一個兩級的前置驅動器,並以 推挽式射極隨耦器來增加對後級的驅動能力,調變電流源主要為一個切換電路,
將電壓信號轉換成電流信號來驅動雷射二極體,使用負電容的技巧來抵消米勒效 應造成的電容性負載,一個Bandgap電流源提供整個電路所需的電流,使電路在 大電流操作之下,對於製程及溫度的變異比較不敏感,電子式量測的結果,符合 SONET OC-192 的眼圖規格,Tr/Tf約為46ps,輸出抖動為 22.2psp-p或2.86psrms, 整個晶片面積為1490×940µm2,在操作電壓3.3V,消耗功率為 1.08W。
文獻參閱
[1] V. Schwarz, B. Willen, H. Jackel, “56Gbit/s Analogue PLL for Clock Recovery,” IEE Electronics Letters, vol. 37, No. 22, pp. 1336-1338, Oct. 2001.
[2] T. Otsuji et al., “20-40-Gbit/s-Cllass GaAs MESFET Digital Ics for Future Optical Fiber Communications Systems,” International Journal of High Speed Electronics and Systems, vol.9, No. 2, pp. 399-435, 1998.
[3] Z. Lao et al., “20-40 Gbit/s GaAs-HEMT Chip Set for Optical Data Receiver,”
International Journal of High Speed Electronics and Systems, vol.9, No. 2, pp.
437-472, 1998.
[4] Ting-Ping Liu, “1.5V 10-12.5GHz Integrated CMOS Oscillators,” VLSI Circuits Design of technical papers, vol.9, No. 2, pp. 55-56, 1999.
[5] A. Tanabe et al., “0.18-μm CMOS 10-Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Function,”
IEEE Journal of Solid-State Circuits, vol.36, No. 6, pp. 988-996, 2001.
[6] H. Knapp et al., “25 GHz Static Frequency Divider and 25Gb/s Multiplexer in 0.12μm CMOS,” IEEE ISSCC, pp. 302-303, February 2002.
[7] M. Fukaishi, K. Nakamura et al., “A 20-Gb/s CMOS Multichannel Transmitter and Receiver Chip Set for Ultra-High-Resolution Digital Displays,” IEEE Journal of Solid-State Circuits, vol.35, No. 11, pp. 1611-1618, 2000.
[8] J. Savoj, B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit With a Half-Rate Binary Phase/Frequency Detector,” IEEE Journal of Solid-State Circuits, vol.38, No. 1, pp. 13-21, 2003.
[9] Jun Cao, M. Green et al, “OC-192 Transmitter and Receiver in Standard 0.18-μ m CMOS,” IEEE Journal of Solid-State Circuits, vol.37, No. 12, pp.
1768-1780, 2002.
[10] Jonathan E. Rogers, and John R. Long, “A 10Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18μm CMOS,” IEEE ISSCC, pp. 254-255, 2002.
[11] Hong-Ih Cong et al., “A 10-Gb/s 16:1 Multuplexer and 10-GHz Clock Synthesizer in 0.25-μm SiGe BiCMOS,” IEEE Journal of Solid-State Circuits, vol.36, No. 12, pp. 1946-1953, Dec. 2000.
[12] M. Meghelli et al., “SiGe BiCMOS 3.3-V Clock and Data Recovery Circuits for 10-Gb/s Serial Transmission System,” IEEE Journal of Solid-State Circuits, vol.35, No. 12, pp. 1992-1995, Dec. 2000.
[13] Y. M. Greshishchev et al., “A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate,” IEEE Journal of Solid-State Circuits, vol.35, No. 12, pp. 1949-1957, Dec. 2000.
[14] Y. M. Greshishchev et al., “SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application,” IEEE Journal of Solid-State Circuits, vol.35, No. 9, pp. 1353-1359, September 2000.
[15] Satoshi Ueno et al., “A Single-Chip 10Gb/s Transceiver LSI using SiGe SOI/BiCMOS,” IEEE ISSCC, September 2001.
[16] G. Georgiou, Y. Baeyens et al., “Clock and Data Recovery IC for 40-Gb/s Fiber-Optical Receiver,” IEEE Journal of Solid-State Circuits, vol.37, No. 9, pp.
1120-1125, September 2002.
[17] M. Meghelli et al., “50-Gb/s SiGe BiCMOS 4:1 Multiplexer and 1:4 Demultiplexer for Serial Communication System,” IEEE Journal of Solid-State Circuits, vol.37, No. 12, pp. 1790-1794, Dec. 2002.
[18] Jafar Savoj, and Behzad Razavi, “High-Speed CMOS Circuit for Optical Receivers,” Kluwer Academic Publishers, 2001.
[19]“SONET OC-192 Transport System Generic Criteria,” Bellcore, GR-1377-CORE, Mar. 1998.
[20] H.-I. Cong, S.M. Logan, M.J. Loinaz, K.J. O’Brien, E.E. Perry, G.D. Polhemus, J.E. Scoggins, K.P. Snowdon, M.G. Ward, “A 10-Gb/s 16:1 Multiplexer and 10-GHz Clock Synthesizer in 0.25-µm SiGe BiCMOS,” IEEE journal of
solid-state circuits, vol. 36, no. 12, Dec. 2001.
[21] “10.7Gbps Laser Diode Drivers,” MAXIM, MAX3930-MAX3932, 2002
[22] Dan H. Wolaver, “Phase-Locked Loops Circuits Design,” Advanced Reference Series & Biophysics and Bioengineering Series, Englewood Cliffs, New Jersey 07632: Prentice Hall, 1991.
[23] Roland E. Best, “Phase-Locked Loops: Design, Simulation, and Applications,” New York: McGraw-Hill, Fourth Ed., 1999.
[24] F. Herzel and B. Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise,” IEEE Trans. Circuits and Systems, Part II, vol. 46, pp. 56-62, Jan. 1999.
[25] W. P. Robins, Phase Nose in Signal Sources, London:Peregrinus, Ltd., 1982.
[26] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and Phase Noise in Ring Oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 790-804, June 1999.
[27] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of Solid-State Circuits, VOL. 31, NO.3, pp. 331-343, March 1996.
[28] J. Craninckx, M. Steyaert, “Wireless CMOS Frequency Synthesizer Design,”
Kluwer Academic Publishers, Boston, 1998.
[29] R. E. Best, “Phase-Locked Loops: Design, Simulation, and Applications,”
New York: McGraw-Hill, Fourth Ed., 1999.
[30] Won-Hyo Lee, Jun-Dong Cho and Sung-Dae Lee, “A High Speed and Low Power Phase-Frequency Detector and Charge-Pump,” IEEE Processing of the ASP-DAC, pp. 269-272, vol.1, 1999.
[31] B. Razavi, Design of Analog Integrated Circuit. New York McGraw-Hill, International Ed., 2001.
[32] B. Razavi, RF Microelectronics. Prentice-Hall Inc., 1998.
[33] M. Danesh et al., “A Q-Factor Enhancement Technique for MMIC Inductors,” Proc. IEEE Radio Frequency Integrated Circuits Symp., pp. 217-220,
April 1998.
[34] B. Razavi, Design of Integrated Circuits for Optical Communications. L.A.
McGraw-Hill, International Ed., 2002.
[35] T. –P. Liu, “A 6.5 GHz Monolithic CMOS Voltage-Controller Oscillator,”
ISSCC Digest of Technical Papers, pp. 404-405, Feb. 1999.
[36] M. Alioto, G. Palumbo, “CML and ECL:optimized design and comparison,”
Circuits and Systems I: Fundamental Theory and Aplications, IEEE Transactions on, vol. 46, Issue. 11 pp. 1330~1331, 1999.
[37] Ritzberyer, G.; Bock, J.; Knapp, H.; Treitinger, L.; Scholtz, A.L., “38 GHz low-power static frequency divider in sige bipolar technology,” Circuits and Systems, IEEE International Symposium, Volume: 4, pp. 413-416, 2002.
[38] Knapp, H.; Wilhelm, W.; Wurzer, M., “A low-power 15-GHz frequency divider in a 0.8-/spl mu/m silicon bipolar technology,” Microwave Theory and Techniques, IEEE Transactions, Volume: 48 Issue: 2, pp. 205-208, Feb. 2000.
[39] Alioto, M.; Di Cataldo, G.; Palumbo, G., “Design of low-power high-speed bipolar frequency dividers,” Electronics Letters, Volume: 38 Issue: 4, pp.
158–160, Feb. 2002.
[40] Alioto, M.; Palumbo, G, “Modeling and optimized design of current mode MUX/XOR and D flip-flop,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, Volume: 47 Issue: 5, pp. 452–461, May 2000.
[41] Nakajima, H.; Sano, E.; Ida, M.; Yamahata, S., “80 GHz 4:1 frequency divider IC using nonself-aligned InP/InGaAs heterostructure bipolar transistors,”
Electronics Letters, Volume: 36 Issue: 1, pp. 34-35, Jan. 2000.
[42] Pulieta, R.; Mensa, D.; Lee, Q.; Agarwal, B.; Guthrie, J.; Jagannathan, S.;
Rodwell, M.J.W., “48 GHz static frequency dividers in transferred-substrate HBT technology,” Electronics Letters, Volume: 34 Issue: 16, pp. 1580-1581, Aug. 1998.
[43] J.F. Ewen et al., “Single-chip 1062 Mbaud CMOS transceiver for serial data communication,” IEEE International Solid-State Circuits Conference, pp. 32-33, 1995.
[44] M. Fukaishi et al., “A 4.25 Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture,”
IEEE J. Solid-State Circuits, vol. 33, pp. 2139-2147, Dec. 1998.
[45] S. Kim et al., “A 960Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL”, IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
[46] Fuji Yang, Jay O’Neill, Patrik Larsson, Dave Inglis, and Joe Othmer, “A 1.5V 86mW/ch 8-Channel 622-3125Mb/s/ch CMOS SerDes Macrocell with Selectable MUX/DEMUX Ratio,” IEEE ISSCC, 2002.
[47] Kyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog-Kyoon Jeong, “A CMOS Serial Link for Fully Duplexed Data Communication,” IEEE JSSC, vol. 30, no. 4, pp. 353-364, Apr. 1995.
[48] Kyeongho Lee, Yeshik Shin, Sungjoon Kim, Deog-Kyoon Jeong, Gyudong Kim, Bruce Kim, and Victor Da Costa, “1.04GBd Low EMI Digital Video Interface System Using Small Swing Serial Link Technique,” IEEE JSSC, vol.33, pp.816-823, May. 1998.
[49] J. Riisboj, “2.5Gb/s laser driver GaAs IC ,” IEEE Journal of Lightwave Technology, vol.11, no.7, pp.1139-1146, July 1993.
[50] Z. Lao et al, “40Gb/s high power modulator driver IC for lightwave communications,” IEEE JSSC, vol.33, no.10, pp.1520-1525, October 1998.
[51] H. Ransijn et al, “A 10Gb/s laser.modulator driver IC with a dual-mode actively matched output buffer,” IEEE JSSC vol.36, no.9, pp.1314-1320, September 2001.
[52] Z.Wang et al, “Integrated laser diode voltage driver for 20Gb/s optical systems using 0.3µm gate length quantum well HEMTs,” IEEE JSSC, vol.28, no.7, pp.829-834, Juky 1993.
[53] M. Meghelli et al, “ High power and high speed InP DHBT driver IC’s for laser modulation,” IEEE JSSC, vol.33, no.9, pp.1411-1416, September 1998.
[54] R. Schmid et al, “40Gb/s EAM driver IC in SiGe bipolar,” Electronics Letters, vol.34, o.11, pp.1095-1097, May 1998.
[55] Garry Link, “High speed semiconductor laser driver circuits,” US patent 5883910, March 16,1999.
[56] R. Schmid et al, “SiGe driver circuit with high output amplitude operating up to 23Gb/s,” IEEE JSSC, vol.34, no.6, pp.886-891, June 1999.
[57] G.C. Chen; W.Z. Chen; R.H. Luo; “A 2.5 Gbps CMOS laser diode driver with preemphasis technique,” ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on , 6-8 pp.65 – 68 Auguest 2002.
[58] A. Maxim, “A 10Gb/s SiGe compact laser diode driver using push-pull emitter followers and Miller compensated output switch,” European Solid-State Circuits, 2003. ESSCIRC '03. Conference on , 16-18 pp.557-560 September 2003.