3. I/Q 正交訊號校正技術
3.4 相位校正電路之實現討論
3.4.3 精確度提升之設計
Pump, CP)之結構通常無法達到對稱，因而不匹配電流(Mismatch Current)會在迴路鎖定時造 成一段固定相位誤差產生，這是因為迴路為了達到動態平衡，使流入與流出之電荷量相等， 測器(Error Phase Detector, EPD)，用以消除這個動態平衡下所產生的相位誤差，其主要構想 在於，通常控制充電泵的脈波訊號是同時被關閉的，若能夠使其關閉時間不一致，則可以 在抵消在正緣處的不一致現象，亦即將此相位誤差由正緣處搬移到負緣處；結合錯誤相位 檢測器與相位檢測器之結構為如圖 3.13(a)所示，除了正常輸入的相位檢測器外，額外使用
錯誤相位檢測器來偵測錯誤相位的資訊，當偵測出有錯誤相位的產生時，由錯誤相位檢測
(w/o EPD calibration)
S2 (w/o EPD calibration)
S1 (with calibration)
S2 (with calibration)
S1
(w/o EPD calibration)
S2 (w/o EPD calibration)
S1
會發生的相位誤差在 33.33 MHz 下仍會發生，證明此段相位誤差是一個固定的相位誤差，
因此若使用在 I/Q 訊號校正機制中，在遇到較高校正基頻頻率時，可能會嚴重降低其校正 精確度，以 50 MHz 為例，其在本地振盪源所產生之誤差將達到 2.7o的誤差量；之後在經 過錯誤相位檢測器的運作與校正後，其所產生之結果如圖 3.14(b)所示，兩訊號之正緣處已 被完全對齊，此時我們再觀察其於 1 GHz 下所鎖定的輸出訊號工作週期，如圖 3.14(d)所示，
可以發現是幾近於完美的 50%，驗證了使用此正緣對齊校正機制的明顯好處，更使得 I/Q 訊號校正機制得以被高精確度的實現在較高的校正基頻頻率上，達到加速校正的效果。
4. 研究成果
本期報告之成果如表格 4-1 所示，在本期之報告中，我們提出了一套 I/Q 訊號校正機制 與類比濾波器的校正設計，與以往研究最主要的不同之處在於，為了適應相當高頻的本地 振盪源，並且相當寬頻的類比基頻電路，我們進一步將本地振盪源與類比基頻電路分開處 理，避免錯誤的相位校正問題，雖然這可能會使得校正時間變得較為冗長，然而卻可以得 到較精確之校正，並且可以適當調整校正之基頻頻率，加速校正速度。
於此接收機其校正電路實現上，因為不是使用 DSP 之方式處理，而是使用工作週期校 正電路之方式，因此可以有較簡潔的電路結構，目前所使用的邏輯運算皆是相當簡潔之邏 輯電路或常見之應用電路，並且我們在這些常見的電路結構上，加上部份創新之設計，提 升這些傳統電路之效能，而這些創新與成果預計在完成設計後投稿國際期刊論文。
表格 4-1 本期報告之創新成果 創新
設計 特色/說明
1 錯誤相位校正機制：新設計之Error Phase Detector，可以校正錯誤相位問題，使用 在DCC或PLL相關電路下，可以提升其精確度或改善Spur之問題。
2 延遲時間延伸機制：含Single Edge Trigger Delay Line，避免了Pull-UP與Pull-DN之 不匹配問題，可提升DCC之精確度與鎖定頻率範圍。
3 結合相位檢測器之重定時序機制：當DCC操作在較高之頻率時，可以降低除頻器所 帶來的Jitter效應，降低輸出訊號之Jitter。
4 LO至Analog Base-Band之I/Q訊號校正機制：將LO降頻後的I/Q訊號於Analog Base Band處轉為倍頻頻率，再以DCC的方式來進行校正，此部份可利用LO頻率與Base Band頻率之比值，來壓抑校正電路之誤差。若希望加速校正時，可提高基頻頻率，
而在校正電路誤差之壓抑方面，可以使用錯誤相位檢測(EPD)機制來壓制。
5 類比濾波器使用SAR演算法校正機制：傳統方式使用Sequential的運算，在此我們運 用SAR的Binary方式來加速完成校正。
本子計劃目前已發表的相關論文成果則列表於表格 4-2，目前多與本地振盪源(鎖相迴 路)之設計有關，這是因應我們所設計的校正機制所需；未來我們將全力將此期所提出之機 制實現出來，進行中的部份主要是接收機的基本電路方塊，並且繼續研究是否有更好的校 正機制與電路設計方式，當中包括了在校正類比基頻電路其 I/Q 訊號路徑時，是否能夠進 一步加速校正之速度，以及是否有其他適合的子電路來操作此一類型的 I/Q 訊號校正，以 完成一個高精確度且快速的 I/Q 校正電路，並應用至各通訊系統上。
表格 4-2 本子計劃之相關論文成果 論文
1 T.-H. Lin, C.-C.Ching, and W.-H. Chiu, “A CMOS Synchronous 50% Duty-Cycle Clock Generator,” submitted to IEEE Trans. Circuits and Systems I.
2 T.-H. Lin, R.-L.Hsu, C.-L. Li, and Y.-C. Tseng, “A 5-GHz 192.6-dBc/Hz/mW FOM, LC-VCO System with Amplitude Control Loop and LDO Voltage Regulator in 0.18-µm CMOS, submitted to IEEE Microwave and Wireless Components Letter (under revision).
3 T.-H. Lin and C.-L. Ti, “Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs,” submitted to IEEE Trans.
Microwave Theory and Techniques.
4 T.-H. Lin and C.-C. Chi, “A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.35-µm CMOS,” IEEE A-SSCC, pp. 91-94, Nov. 2006.
5 C.-L. Ti and T.-H. Lin, “A 2.4-GHz 18-mW Two-Point Delta-Sigma Modulation Transmitter for IEEE 802.15.4,” accepted to IEEE VLSI-DAT, April 2007.
6 R.-L. Syu, C.-L. Li, and T.-H. Lin, “A 5-GHz CMOS Frequency Synthesizer with Triode Regime Biased LC-VCO for Low Phase Noise,” VLSI Design/CAD Symposium, pp.
125-128, Aug. 2006.
參考文獻
[1] F. Lee, D. Wentzloff, and A. Chandrakasan, “An Ultra-Wideband Baseband Front-End,”
IEEE RFIC Symposium, pp. 493-496, June. 2004.
[2] Chia-Hsin Wu, Chang-Shun Liu, and Shen-Luan Liu, “A 2GHz CMOS Variable-Gain Amplifier with 50dB Linear-in-Magnitude Controlled Gain Range for 10GBase-LX4 Ethernet,” IEEE ISSCC, pp. 484–485, Feb. 2004.
[3] S. Pavan, Y. P. Tsividis, K. Nagaraj, “Widely Programmable High-Frequency Continuous-Time Filters in Digital CMOS Technology,” IEEE J. Solid-State Circuits, pp.
503–511, April. 2000.
[4] Navid Foroudi and Tadeusz A. Kwasniewski, “CMOS High-Speed Dual Modulus Frequency Divider for RF Frequency Synthesis,” IEEE J. Solid-State Circuits, pp. 93-100, Feb. 1995.
[5] J. Harrison and N. Weste, “A 500 MHz CMOS Anti-Alias Filter Using Feed-Forward Op-Amps with Local Common-Mode Feedback,” IEEE ISSCC, pp. 132–133, Feb. 2003.
[6] T. Zhang, W.R. Eisenstadt, and R.M. Fox, “A Novel 5GHz RF Power Detector,” ISCAS
2004, pp. 897-900, May. 2004.
[7] Hong-Sun Kim, M. Ismail, and H. Olsson, “CMOS Limiters with RSSIs for Bluetooth Receivers,” MWSCAS 2001, pp. 812-815, Aug. 2001,
[8] I. Elahi, K. Muhammad, and P. T. Balsara, “I/Q mismatch compensation in a 90nm low-IF CMOS receiver,” IEEE ISSCC, pp. 542-616, Feb. 2005.
[9] I. Elahi, K. Muhammad, and P. T. Balsara, “I/Q mismatch compensation Using Adaptive Decorrelation in a Low-IF Receiver in 90nm CMOS Process,” IEEE J. Solid-State, pp.
395-404, Feb. 2006.
[10] M. Hajirostam and K. Martin, “An analog-digital adaptive image-reject technique for quadrature receivers,” in Proc. Eur. Conf. Circuit Theory and Design 2005, pp. 281-284, Aug. 2005.
[11] R. Schaumann and M. V. Valkenburg, Design of analog filters. Oxford University Press, Inc, 2001.
[12] T. Oshima, K. Maio, W. Hoie and Y. Shibahara, “Novel Automatic Tuning Method of RC Filters Using a Digital-DLL Technique,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp.
2052 - 2054, Nov. 1985.
[13] G-K Dehng, J-M Hsu, C-Y Yang, and S-I Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1128 - 1136, Nov. 1985.
[14] S. Lerstaveesin, et. al, “A Complex Image Rejection Circuit With Sign Detection Only,”
IEEE J. Solid-State Circuits, vol. 41, pp. 2693-2702, Dec. 2006.
[15] L. Der, et. al, “A 2-GHz CMOS image-reject receiver with LMS calibration,” IEEE J.
Solid-State Circuits, vol. 38, pp. 167-175, Feb. 2003.
[16] T.-H. Lin and C.-C. Chi, “A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.35-µm CMOS,” IEEE A-SSCC, pp. 91-94, Nov. 2006.
附錄 A. 論文成果發表摘要
IEEE A-SSCC, Nov. 2006
「A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.35-µm CMOS」
T.-H. Lin and C.-C. Chi
Abstract- a 50% duty-cycle correction (DCC) circuit is reported in this paper. The proposed
DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output whose pulse width is adjusted to half of the signal period by the delay detector. Meanwhile, the input phase information is maintained. The circuit is implemented in a 0.35-µm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing test method is adopted. This circuit operates from 70 MHz to 490 MHz, and accommodates duty cycles ranging from 10% to 90%. The output signal is corrected to 50% ± 2%. Operated from a 3.3-V supply, the circuit dissipates 8 mA at 490 MHz.成果
Process TSMC 0.35-µm CMOS
Supply Voltage 3.3 V
Current Consumption 6 ~ 8 mA Operating Frequency 70 ~ 490 MHz Output Duty-Cycle Error < ± 2 %
Max. Input Duty Cycle > 90%
Min. Input Duty Cycle < 10%
晶片圖
PFD,CP
Loop Filter Mixer
Delay Element
PFD,CP
Loop Filter Mixer
Delay Element
IEEE VLSI-DAT, April 2007
「A 2.4-GHz 18-mW Two-Point Delta-Sigma Modulation Transmitter for IEEE 802.15.4」
C.-L. Ti and T.-H. Lin
Abstract-
a 2.4-GHz two-point modulation transmitter (TX) is reported in this paper. The TX is based on a delta-sigma fractional-N PLL to reduce chip area and power consumption. In addition, the chosen architecture prevents the transmission data rate from being limited by the PLL bandwidth. To alleviate the non-linearity problems of a conventional fractional-N PLL, linearization techniques are adopted. The TX is designed to operate in the 2.4-GHz ISM band, and is capable of delivering a date rate more than 2 Mbps. Implemented in the TSMC 0.18-µm CMOS process, the TX consumes 18 mW under a 1.4-V supply voltage.成果
Process TSMC 0.18-µm CMOS
Supply Voltage 1.4 V
Frequency Band 2.4 GHz ISM Band
Power Consumption < 18 mW
PLL Phase Noise -123 dBc/Hz @ 1 MHz
Settling Time 20 µs
Transmit Data Rate > 2 Mbps (up to 4 Mbps)
Spectrum mask Spectrum mask Spectrum mask Spectrum mask
晶片圖
VCO Output
Buffers Divider & PFD MASH
Charge Pump
Loop Filter
3-wire Interface
VCO Output
Buffers Divider & PFD MASH
Charge Pump
Loop Filter
3-wire Interface
VLSI Design/CAD Symposium, Aug. 2006
「A 5-GHz CMOS Frequency Synthesizer with Triode Regime Biased LC-VCO for Low
Phase Noise」
R.-L. Syu, C.-L. Li, and T.-H. Lin
Abstract- to reduce phase noise degradation from oscillator tail current sources, this paper
presents employing triode MOS transistors to bias an LC-VCO. The VCO system also includes an amplitude control loop and a voltage regulator to endure PVT variations and to enhance circuit PSRR. Fabricated in a 0.18-µm CMOS process, the measured results show the adopted topology achieves a better phase noise than the conventional saturation current source does. At 5.181 GHz, the VCO system demonstrates a phase noise of -104.8 dBc/Hz at 100-kHz offset, and -127.1 dBc/Hz at 1-MHz offset, while dissipates 4.2 mA from a 1.8-V supply voltage. The corresponding FOMs at 100-kHz and 1-MHz offset are 190.3 and 192.6 dBc/Hz/mW, respectively.成果
Process TSMC 0.18µm CMOS
Supply Voltage 1.8 V
Frequency Tuning 5.6% (5.25 GHz ~ 5.55 GHz) VCO 0 mW ~ 16.5 mW
VR 0.34 mW
PLL 15 mW
Power Consumption
Total 15.84 mW ~ 31.84 mW
Phase Noise -104 dBc/Hz (100 kHz) -127.1 dBc/Hz (1 MHz)
Frequency Offset [Hz]
Phase Noise [dBc/Hz]
-98.2
Frequency Offset [Hz]
Phase Noise [dBc/Hz]
-98.2
Frequency Offset [Hz]
Phase Noise [dBc/Hz]
10M
Frequency Offset [Hz]
Phase Noise [dBc/Hz]
10M
Frequency Offset [Hz]
Phase Noise [dBc/Hz]
10M
Frequency Offset [Hz]
Phase Noise [dBc/Hz]
-98.2
VCO Current [mA]
192
VCO Current [mA]
192