The global wiring is becoming a fundamental roadblock to true scaling beyond the 0.25 µm node technology, as shown in Fig. 1-1 [1,2]. The variation disparity between the transistor gate delay and the global wiring (interconnect) delay is evident.
However, the interconnect delay can be improved by repeaters, which have the effect of global buffering because of the loose pitch structure of back-end-of-line (BEOL) metallization [2] and interconnect length reduction [3]. For the high performance design, such as multi-GHz microprocessors, the interconnect delay is directly related to the resistance-capacitance (RC) time constant [2,3], which is defined in terms of the circuit response, as given by Eq. (1-1):
where Vout(t) is the output voltage of the circuit, t is the time, and R and C are lumped total of resistances (except that of load transistor resistance) and capacitances associated with the dielectric of the circuit, respectively [3]. Thus, RC delay is the time when Vout(t＝RC) attains a value of 63.2% of Vout(maximum). One can
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permittivity, interconnect length, interconnect thickness, metal width, and ILD width, respectively. Note that ε＝kε0, where k is the dielectric constant (k-value) of ILD and ε0 is the permittivity of free space [3]. Thus, besides using a lower resistivity metal for interconnect wiring and a lower dielectric constant material for the ILD, one can also reduce the RC delay by designing the circuit to accommodate shorter interconnects and wider wires. However, a longer interconnect becomes inevitable because larger chip size and multilevel interconnection are both needed to meet the requirements of the increased functional complexity and packing density of the integrated circuits (ICs) [4]. Moreover, wider wires are short-term solution for reducing the RC delay because of the concerns of smaller IC area and higher IC throughput. Therefore, using a lower resistivity metal for the interconnect wiring and a lower dielectric constant material for the ILD becomes a feasible approach for reducing the interconnect RC delay.
1-2 Cu Metallization
Copper (Cu) has been widely used as an interconnect wiring in ultra-large scale integrated (ULSI) circuits. Compared with the conventional aluminum-based (Al-based) wires, Cu metal reduces the electrical resistance of interconnect lines because of its lower electrical resistivity; moreover, Cu line also sustains a higher current density because of its higher thermal conductivity and higher melting point, as shown in Table 1-1. Furthermore, Cu exhibits excellent resistance to electromigration, stress-migration, and hillock formation. However, there are a number of integration and reliability issues needed to be solved before the Cu metallization can be successfully used in the silicon-based (Si-based) ULSI circuits.
Cu readily drifts into SiO2 and ILDs deposited by spin-on or plasma-enhanced
chemical vapor deposition (PECVD) with an applied electric filed of 1 MV/cm at temperatures as low as 100oC [5-9], resulting in poor dielectric breakdown lifetime.
Cu also has a very high temperature-independent diffusion coefficient (Do) of 0.04 cm2/sec in Si [10]. In addition, Cu is a deep-level dopant in Si and forms a number of acceptor and donor type generation-recombination centers within the forbidden band gap, leading to induce a large leakage current [4,11]. Since it is inevitable to use metallic and/or dielectric barriers to encapsulate the Cu metallization in order to suppress the diffusion/drift of Cu into the active region of the electronic devices, a number of issues regarding the encapsulation scheme must be addressed, such as the Cu/barrier interface-diffusion arisen from electromigration, Cu/barrier interface-reaction during the deposition of the barrier layer, and poor breakdown lifetime of dielectric barrier resulting from the Cu diffusion [12,13]. Notably, the dielectric breakdown lifetime can be improved by using an ammonia-plasma (NH3-plasma) treatment on the Cu-surface prior to the cap α-SiN (amorphous silicon-nitride) deposition on a Cu-comb capacitor [13]. Before making a successful integration of the barrier film and the Cu metal with a plasma-treated surface, fundamental properties, such as plasma induced Cu-surface roughness and chemical bonding of the plasma-treated Cu-surface, must be first explored. In this thesis, we investigate the effects of oxygen-plasma (O2-plasma) and nitrogen-plasma (N2-plasma) treatments on the Cu-surface.
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(Cr-based), and molybdenum-based (Mo-based) metallic barriers [14-27]. However, the conventional α-SiN film (k~7) is still the primary dielectric material used for cap-barrier and etch stop layer (ESL) in the Cu metallization of production-chip [28].
Although a modified α-SiN film (k~5.4) was developed by low-pressure chemical vapor deposition (LPCVD) using hexachlorodisilane (HCD) [29], it is still desirable to replace α-SiN with dielectric materials of lower k-value (k<5) in order to further reduce the effective dielectric constant of the Cu interconnection line. In recent years, a number of studies have been reported regarding the thermally stable and Cu-diffusion restrained low-k silicon-carbide-based (SiC-based) films deposited by PECVD using organosilicate gases [30-39]. The PECVD amorphous silicon-carbide (α-SiC), amorphous silicon-nitricarbide (α-SiCN), and amorphous silicon-oxycarbide (α-SiCO) have received extensive attention for applications as Cu cap-barrier and ESL in Cu metallization because of their lower k-value, better etching selectivity with organosilicate glass (OSG), robust chemical mechanical polishing (CMP) strength, good photoresist poisoning resistance, higher anti-reflective ability, and superior properties as a Cu barrier/passivation layer in terms of Cu-restraint, electromigration resistance, and Cu-hillock density [35,38-42].
For the study of the SiC-based dielectric barrier films in this thesis, we investigated the thermal stability, physical property, barrier characteristic, and electrical performances (leakage current, leakage mechanism, breakdown field, and breakdown mechanism) of the PECVD α-SiCN, α-SiC, and α-SiCO films deposited using trimethylsilane [(CH3)3SiH, 3MS], tetramethylsilane [(CH3)4Si, 4MS], or octamethylcyclotetrasiloxane {[(CH3)2SiO]4, OMCTS} organosilicate gases. Table 1-2 summarizes the α-SiCN, α-SiC, and α-SiCO dielectric barrier films studied in this thesis.