In order to minimize the variation between each SWNT, TFTs based on SWNT networks consisting of large number of SWNTs rather than individual SWNT are fabricated to average individual SWNT deviation by SWNT networks. In 2003, Duan et al. proposed TFTs fabricated with aligned CNTs as channel by using flow-directed alignment method [55]. This work offered a new direction for high performance TFTs.
Since then, many studies of CNT network TFT are published.
CNT network TFTs could be divided to two groups by the way CNT networks
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orient. Y. Huang showed that parallel CNT array could be formed by using fluidic alignment and flow direction control with surface-patterning of PDMS mold [56].
CNT orientation also could be controlled by the direction of gas flow with a tilt angle [57-58]. M. Engel used evaporation self-assembly method to orient CNT arrays [59].
The CNT array also could be fabricated on a designed array of catalysts by using PECVD [60]. A.D. Franklin proposed aligned CNT array FETs with current density >
40 uA/μm at on/off ratio >105 [61], however, the CNT array needed to transfer from quartz to silicon wafers. This CNT transfer process preserved CNT density and alignment by using thermal release adhesive tape, but the process was complex and unsuitable for large scale manufacture [62]. The drawback of aligned CNT network is that the assembling process is complex and lack of precise control of CNT alignment.
Although CNT arrays would align along specific direction, intersections between CNTs still exist. Papers listed above about aligned CNT network as device channel are shown in Table 1-1.
Due to the simplicity for the formation of CNT network, random CNT network TFTs which CNTs orient with no preferential directions are suitable for large scale fabrication. A large number of CNTs average deviation of individual CNT. E.S. Snow reported a random SWNT networks TFTs with field-effect mobility of 10 cm2/Vs at on/off ratio > 105 for low CNT density and field-effect mobility > 100 cm2/Vs at on/off ratio < 10for high CNT density [63-64]. CNT powder dissolved in SDS [65] or EAQ/DMF [66] solution with gradient ultracentrifugation were used to separate CNT bundles and improved the uniformity of CNT networks formed by spin-coating method. In addition, aminosilane such as aminopropyltriethoxy silane (APTES) was used to functionalize the SiO2 [67] and HfOx [68] surface to achieve high density and uniform CNT network due to its well-known affinity to the CNTs.
The simple way to fabricate random CNT network is performing spin-casting
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method. However, about 1/3 metallic and 2/3 semiconducting CNTs both exist in network. Once metallic CNT conducting paths bridge channel, the on/off ratio would significantly degrades. Recently some works studied percolation theory [69-71] which was studied in the formation of CNT conducting paths in the network. J. N. Coleman reported an organic composite consisted of mixture of organic polymer and CNTs [72].
The CNT concentration increased with the significant increase of conductivity of organic composite which was in agreement of percolating behavior. L. Hu studied the sheet conductance and transparency of CNT network as a function of CNT density [73]. When the CNT density is above the percolation threshold, conductivity of CNT network increases obviously. This means the CNT conducting paths are formed. On the other hand, the percolation theory is not suitable for study of optical transparency of CNT network since transparency is determined by CNT excitation rather than CNT conductance. H. E. Unalan found that device performance of CNT TFT is limited by metallic CNTs as percolation density of metallic CNTs is much below percolation threshold of conducting paths [74]. S. Kumar studied a computational model containing ballistic and diffusive transport limit to analysis the conductance of CNT network [75]. A. Behnam performed Monte Carlo simulations to study the geometry-dependant resistivity of CNT films and found that the lowest resistivity occured in the partially aligned CNTs rather than perfectly aligned CNTs [76]. J.
Hicks reported the CNT length distribution dependent on the resistivity for junction-resistance-dominant and intrinsic-resistance-dominant CNT networks, respectively [77]. S. Seppälä computed percolating network of CNT bundles due to van der Waals interaction for varying bundle length and bundle density. This work discovered semiconducting CNT bundle paths were more frequently formed for low density comparing with ordinary SWNT networks [78]. V. K. Sangwan performed experiments and simulations to determine that the percolating CNTTFT with mobility
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of 5~50 cm2/Vs at on/off ratio > 103 at L > 70 μm and W= 50 μm for CNT density of 0.54~0.81 CNTs/μm2 [79]. Table 1-2 shows papers discussing random CNT networks as device channel.
1-5. Motivation
Recently, most percolation issues were emphasized on the conductance of CNT network rather than device performance of CNT network TFTs. Although some studies showed experimental electrical characteristics of devices fabricated with CNT percolating networks, a few works focused on the analytical study of properties of CNT networks TFT. This thesis systematically studied the effects of CNT property and device geometry on device performance based on CNT networks for both experiments and simulations. By studying the percolating CNT network with proper fabrication condition and device structure, the suitable device design and control could be obtained.
This thesis studies the carbon nanotube network thin film transistor (CNTN TFT) structure consisting of an extra poly-Si gate as local bottom gate instead of using heavily-doped Si substrate as a back gate. The merit of back gate structure is easy to fabricate. However, the back gate structure would not control each device on whole wafer respectively at single operation. Besides, devices with back gate structure need thicker gate dielectric layer to prevent gate leakage since that source/drain is totally overlapped by back gate. But increasing gate dielectric thickness would degrade the gate-to-channel control ability.
To improve the drawback of back gate structure, some papers proposed the idea of top-gated CNT TFT [39]. Though top gate structure would control each device respectively, the surface coverage of top gate dielectric layer and gate leakage are
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severe issues. First, the gate dielectric would not be formed by thermal oxide since the CNT network which belongs to back-end process is formed prior to gate dielectric.
Other methods to form gate dielectric layer would be sputter, plasma enhanced chemical vapor deposition (PECVD), E-gun evaporation, atomic layer deposition (ALD), and so on. But note that for some process such as PECVD would strongly damage CNTs by plasma bombardment. G. Zhang presented a plasma hydrocarbonation reaction to selectively etch metallic CNTs and remain semiconducting CNTs [80]. The key process to selective etch metallic CNTs was to use methane plasma instead of hydrogen plasma due to its moderate reactivity.
Recently ALD is a popular process to form the gate dielectric to cover on CNT network. However, ALD process is still difficult to grow high quality of thin film on CNT network since the chemical inert exterior surface of CNTs would retard the precursor to absorb on. Therefore, to form perfect ALD gate dielectric layer on CNT network needs another CNT functionalization to improve the surface coverage of top gate dielectric layer and prevent gate leakage. B Damon made NO2 functional group attach to nanotube surface to improve the ALD Al2O3 layer uniformity due to the reactivity of precursors enhencement [81-82].
The second issue of top gate structure is gate leakage. In order to avoid damaging CNTs, the source/drain fabrication also needs to prevent CNTs exposing in the plasma atmosphere. Therefore, the metal source/drain definition process is performed by lift-off method rather than metal dry etching. The disadvantage of lift-off method is the sharp edge of source/drain affects the conformal ALD gate dielectric and makes gate dielectric locally thinner near sharp edge of source/drain.
This locally sharp region further enhances the electric field and then increases the probability of gate leakage.
In this work, the CNTN TFT with poly-Si bottom gate which is compatible to
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horizontal furnace of front-end process is studied. Bottom gate structure would eliminate the gate dielectric coverage issue since the gate dielectric formation is prior to CNT network fabrication. There is no need to employ other functionalization to CNTs. The reduction of overlap between bottom gate and source/drain could decrease the parasitic capacitance and scale the gate dielectric thickness to operate device at low operation voltage. Besides, devices with bottom gate structure would control single device at single operation.