2.3-1. Electrical characteristics of pMOSFETs with and without fluorine incorporation
The C-V curves in Fig. 2-6 indicate not obvious change of EOT with and without fluorine sample, this means that fluorine atoms doesn’t break Hf-F bond and then
causes dielectrics degradation [10]. And we can also observe that C-V curve in
F-incorporated sample show shift toward positive Vg direction. Similar phenomenon
was observed in Id-Vg characteristics show in Fig. 2-7. This is point out that decrease
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of positively charged traps or increase of negatively charged traps [8, 9, 13]. In Fig.
2-7 and Fig. 2-8 we also observe both drain current and transconductance have a
apparent improvement in F-incorporated sample. Fig. 2-9 and Fig. 2-10 depict the
results of driving current and maximum transconductance versus different channel
length. When channel length becomes shorter, the improvement is more apparent.
Fig. 2-11 indicates the sub-threshold swing for devices with and without fluorine
incorporation. We find that sub-threshold swing versus channel length. We find that
sub-threshold swing in F-incorporated sample is smaller than it in control sample.
This implies that this dose of fluorine doesn’t cause severe damage in silicon bulk, on
the other hand it makes the interface better. Fig. 2-12 shows the threshold voltage
versus channel length. Threshold voltage shift toward positive Vg direction was also
observed in F-incorporated sample. Fig. 2-13 and Fig2-15 show the maximum
transconductance versus various channel width and area .Fig. 2-14 and Fig. 2-16 show
the threshold voltage versus diverse channel width and area. We can see that
F-incorporated sample has obvious improvement on maximum transconductance no
matter in different channel length, width and area. And threshold voltage shift toward
positive Vg direction also observe in F-incorporated sample. The driving current and
transconductance of F-incorporated are higher than control sample. This is because
less interface state existed in F-incorporated sample, and the higher mobility we get.
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We can prove that by charge pumping method, in Fig 2-17. express charge pumping
current for device with and without fluorine incorporation. We observe that charge
pumping current decreases in F-incorporated sample. This implies a lot of dangling
bond could be fixed by fluorine ion and therefore reduces interfacial layer. And then
we can extract the value of Nit by equation (2-1). Then we get Nit values of
6.3067x1010cm-2 and 5.3926x1010 cm-2 with and without fluorine incorporation
respectively.
Fig. 2-18 shows that mobility versus effective electric field, we find the higher
mobility we get in F-incorporated sample. This is also caused by fluorine ion fixed
dangling bond in the interfacial layer. But using split-CV method wouldn’t calculate
short channel device because we the capacitance is too small and disturbance is too
large, then we can’t get it by HP4284 LCR meter. Therefore, we only can measure the
large dimensional device. Fig 2-19 reveals that leakage current seems not to be
increased for device with and without fluorine incorporation.
2.3-2. Conduction mechanism of pMOSFETs with HfO2
/SiON gate stack
The carrier type involved in the leakage current through HfO2/SiON dielectric
layers have also been investigated for unstressed pMOSFETs, using carrier separation
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method [14]. The contributing carrier of the gate leakage current can be separated into
holes and electrons. Fig. 2-20 shows carrier separation results under the inversion
region, and Fig. 2-21 shows carrier separation results under the accumulation region
for P+-gated PMOSFETs with HfO2/SiON gate stack, both with and without fluorine
incorporation. It is found that the source/drain current ISD dominates the leakage
current under inversion region, and the substrate current IB dominates the leakage
under accumulation region. This indicates holes from S/D that tunnel through gate
dielectric is the dominant component of conduction mechanism under inversion
region , while electrons from gate electrode that tunnel through gate dielectric is the
dominant component of conduction mechanism under accumulation region.
This could be explained by band-diagrams shown in Fig. 2-22(a) and carrier
separation experiment shown in Fig. 2-22(b). The substrate current IB corresponds to
the electron current from the gate , while the source/drain current ISD corresponds to
the hole current from Si substrate under inversion region. Electron supply from the
gate conduction band in pMOSFETs is limited by the generation rate of minority
electrons in p+ gate. In other words, the probability of carriers from S/D that tunnel
through gate dielectric is strongly affected by tunneling distance and barrier height
[15]. Because of the asymmetry of the HfO2/SiON band structure , it is more difficult
for electrons to tunnel through gate dielectrics compared with holes. In pMOSFETs ,
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hole current from the channel is the predominant injection current under stressing.
The leakage component under accumulation region can also be explained by
band-diagrams shown in Fig. 2-23(a), and the current component flow in carrier
separation experiment is shown in Fig. 2-23(b).
In Fig. 2-24 and Fig. 2-25 , the gate current Ig as a function of Vg for the
HfO2/SiON layer is measured from temperature up to 125℃, both under inversion
region and accumulation region for two samples. The current is temperature
dependent that increases with increasing temperature. This implies that the conduction
mechanism of current is trap-related, i.e., trap-assisted tunneling (TAT). Frenkel-poole,
etc.
The gate leakage current for devices with HfO2/SiON gate stack is composed of
two types of current, i.e., hole current and electron current. To determine the
conduction process in the HfO2/SiON dielectric, Frenkel-poole (F-P) plots are fitted
for hole current and electron current, respectively, for both samples.
The current from Frenkel-poole emission is of the form:
exp(2 B)
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⇒ intercept gives the Barrier height ( B
B
permittivity, εinsis HfO2 dielectric constant, kB is Boltzmann constant , and T is the
temperature measured in Kelvin.
As shown in Fig. 2-26 and Fig. 2-27, under inversion region, excellent linearity for
each current characteristic has been observed for both samples. This tendency
indicates that both samples exhibit the Frenkel-Poole conduction mechanism for the
gate leakage current. Both the electron and hole conduction mechanisms are the same,
and the result agree well with the F-P conduction mechanism. Barrier height ΦB and
dielectric constant εinsof HfO2/SiON can be calculated. The
HfO2
ε valre is found to be
~ 14.7 and ~14.4 for the control and F-incorporated samples, respectively.
The ΦB for the hole traps in the control sample and F-incorporated sample is about
1.47eV and 1.51eV, respectively. On the other hand, for electron traps, the ΦB of the
control sample and F-incorporated sample are about 1.59eV and 1.62eV, respectively.
The ΦBto be discussed in this chapter is the “effective＂ value that is representative
of the HfO2/SiON gate stack [15]. We consider the case when the injected carriers
flow across HfO2/SiON by hopping via the trap sites with energy barrier ΦB, whose
value depends on the fabrication process [16]. These experimental results indicate that
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the energy level for traps in the control sample is similar to that of the F-incorporated
sample, and the energy barrier ΦB for holes is clearly lower than that for electrons
about 0.12eV in both samples.
2-4 summary
In this work, the initial electrical properties of the devices are smaller affected by
fluorine incorporation, such as absolute threshold voltage is smaller and CV curve
shifts toward positive Vg direction. We verify that appropriate fluorine incorporation
doesn’t degrade the interface and dielectric quality, and it can enhance mobility and
drive current of the device. We use carrier separation to verify that devices with and
without fluorine incorporation, we found gate leakage current is the same with both
devices. And conduction mechanism is Frankel-Poole emission.
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