Two modes of biasing the asymmetrical PMOSFET structure are shown in Fig.
3.7. According to the standard test configuration for PMOSFET, the source is
grounded while the drain is biased with a negative voltage. [1] So, in the forward mode shown in the Fig. 3.7 the side with a shallower extension serves as the drain, and in the reverse mode the drain is switched to the side with deeper extension.
Figure 3.8 (a) shows the transfer characteristics of an asymmetric PMOSFET of Type C. The channel length is 0.3 μm. In the figure the solid lines represents the forward mode while the dashed lines represents the reverse mode. We can observe that the forward mode has slightly better characteristics in terms of higher drive current and transconductance. The sub-threshold swing (SS) is about 86 mV/decade.
The drain induced barrier lowering (DIBL) of forward mode is about 58 mV/V while the reverse mode is 65 mV/V. DIBL is also better with the forward mode. However, the differences mentioned above are not significant as expected. Dependences of DIBL and transconductance versus channel lengths are discussed later in Sec. 3-3. Fig.
3.8 (b) shows the transfer characteristics of a Type-D device with channel length the same as the device characterized in Fig. 3-8(a). In the figure we can see that the forward mode and reverse mode have more appreciable difference in DIBL. As described in last chapter, Type-D device has deeper source extension than Type-C under forward mode of operation. This explains the more profound DIBL difference between the two modes in Fig. 3-8(b).
As can be seen in Fig. 3.8 (c), the transfer characteristics of channel length below 0.3 μm show significantly punch-through behavior. The gate loses effective control of the channel, especially as a high drain bias is applied. The etch-induced recession mentioned above is certainly one of the factors responsible for the damage.
Additional techniques for suppressing the short-channel effects should be introduced to reach the short channel below 0.1 μm.
Figure 3.9(a) shows the output characteristics of a nominal symmetrical PMOSFET, which uses double-patterning technique to define the gate length and the extensions at two sides are designed with the same depth. However, difference in drive current between the two modes is observed and the reverse mode shows degraded drive current as much as 9%. Figure 3.9 (b) shows the output characteristics of an asymmetric Type-C PMOSFET with identical channel length. As mentioned in Chapter 2, the drain extension of this device was formed with a relatively low implantation energy of 10 keV. In this case the reverse mode further degrades the drive current by the maximum value of 24 %.
The degradation of the drive current is resulted from the increase in the source-drain series resistance. In the discussion of long channel MOSFET current, usually the effect of S/D resistance can be ignored. However, in a short-channel device, the source-drain resistance can be an appreciable fraction of the total series resistance. Theoretically the nominal symmetrical device characterized in Fig. 3.9(a) should not exhibit asymmetrical I-V characteristics shown in the figure. From the SEM analysis given in last section, obviously the degradation in reverse mode is caused by the asymmetrical etched profiles of the double patterning technique. The asymmetrical extension profile would further worsen the situation, as evidenced in Fig. 3.9(b).
The effect of source-drain resistance can be understood with the equivalent
circuit shown in Fig. 3.10. A source resistanceR and a drain resistances R are assumed d to connect an intrinsic MOSFET to the external terminals where V andds Vg are applied. The internal voltage areVds'andVgs'for the intrinsic MOSFET. One can write the following relations:
According to the above equations, when a MOSFET is operated, the decrease in the overdrive voltage Vgs' is mainly affected by the source resistance. While operating in saturation region, the drive current is correlated with overdrive voltage (Vgs’-Vth) rather than the drain voltage. In other words, the drive current is affected more seriously by the source resistance. In Fig. 3.9(a), the degradation under reverse mode indicates the recessed side contributes more resistance than the other side. This is reasonable, since the recessed junction has a longer distance (along the sidewall of the recess region) to reach the channel edge, as shown in Fig. 3.6. Additional degradation is observed in Fig. 3.9(b) for the asymmetrical device due to the shallower extension depth in the recessed side.
Figure 3.11 (a) and (b) is the output characteristics of the devices with nominal symmetrical S/D and Type-C devices, respectively, measured with a relatively wide drain bias range to illustrate the breakdown behavior. The channel length is 0.3 mμ . As can be seen from the figures, breakdown occurs in the short-channel MOSFET when the drain voltage exceeds a certain value. For the nominal symmetric PMOSFET, difference between the breakdown voltage of forward mode and reverse
modes is small. For the asymmetric MOSFET, though the difference of breakdown voltage between the two modes is also small, the breakdown current of reverse mode is appreciably higher than that of the forward mode. This implies that forward mode has better hot carrier reliability than the reverse mode. Although in this work the unexpected etch-induced recessed phenomenon occurred, it is still confirmed that a reduction in the depth of drain extension junction region during operation can improve the hot carrier reliability. Substrate current can be another indicator for the hot carrier effect. From Fig. 3.12, substrate current of reverse mode is higher than that of forward mode for the asymmetrical device characterized in Fig. 3.11(b). The breakdown process in a PMOSFET is shown in Fig. 3.13. In the process the holes gain energy from the field as they move forward along the channel. Before losing energy through collisions, a number of the holes posses high kinetic energy and are capable of generating secondary electrons and holes by impact ionization. The generated holes are attracted to the drain, adding to the drain current, while the electrons are collected by the substrate contact, resulting in a substrate current. The substrate current in turn can produce a voltage drop from the spreading resistance in the bulk, which tends to forward-bias the source junction. This lowers the threshold voltage of the MOSFET and triggers a positive feedback effect, which further enhances the channel current. The results shown in Fig. 3.11(b) and 3.12 confirm that a shallower drain extension can indeed reduce the field strength in the channel and suppress the associated hot-carrier effects.
Typical capacitance-voltage characteristics of the devices are shown in Fig. 3.14.
Serious poly-Si gate depletion effect is observed. The capacitance in the inversion region does not return to the maximum oxide capacitance recorded in the accumulation region. Instead, the inversion capacitance exhibits a local maximum value, Cmax, at Vg of around -1.5V. This is a feature of poly depletion effect [1], and the local maximum capacitance is dependent on the effective doping concentration of the poly-Si gate. The higher the doping concentration, the less profound the gate depletion effect is and the local maximum capacitance becomes closer to the oxide capacitance. Based on the analysis of poly-Si depletion effect [1], the relationship between Cmax and the doping concentration of the poly-Si gate, Np, can be extracted from the following equation:
From the equation, the active doping concentration is about 2×1018 cm , −3 which is far less than the typical value (~1020cm-3) in the poly-Si gate. This might be related to the activation step which was carried out with spike-RTA anneal with maximum temperature of 1000 ℃. Further optimization in the activation step is needed to suppress such effect.