3-1 Introduction
In this chapter, the detailed fabrication processes of flip-up micro scanning mirrors are depicted. The mirrors are fabricated on the SOI wafers due to its flatness.
Using SOI wafers can also reduce the complexity of the process. There are only three masks in the process. One is for patterning the front side device layer, one is for the back side handle layer of the substrate and the other is for upper comb fingers made by SU-8 photoresist. The SU-8 photoresist provides not only good mechanical properties for the structure, but also relatively simple fabrication processes. The handle layer of the SOI wafers is used for mechanical connection as depicted in Chapter 2, as well as for enhancing the strength of the structure to avoid bending and improve the mirror flatness. The buried oxide is the sacrificial layer. The nitride layer deposited on the device layer is the hard mask for the DRIE process. Gold is deposited for electrical connection and good reflectivity. The detailed fabrication processes are described in the following. Finally, fabrication issues are discussed.
3-2 Fabrication flow
Figure 3-1 shows the schematic of the fabrication flow. The device layer of the SOI wafer is 5 μm thick, the buried oxide layer is 2 μm thick and the substrate is 400 μm thick. The device is fabricated at the Nano Facility Center of National Chiao Tung University and the National Tsing Hua University Center for Nanotechnology, Materials Science, and Micro Systems.
(a) RCA cleaned SOI wafer (step A)
(b) Front side nitride and back side oxide deposition (step B, step C)
(c) Front side nitride patterning (step D, step E)
Figure 3-1. Fabrication flow Buried oxide Silicon
Buried oxide LPCVD nitride PECVD oxide Silicon
Buried oxide LPCVD nitride PECVD oxide FH 6400 photoresist Silicon
(d) Back side oxide patterning (step F, step G, step H, step I)
(e) SU-8 photoresist patterning (step J)
(f) Front side ICP (step K)
Figure 3-1. Fabrication flow (continued) Buried oxide LPCVD nitride PECVD oxide
Silicon
Buried oxide LPCVD nitride PECVD oxide SU-8 photoresist Silicon
Buried oxide LPCVD nitride PECVD oxide SU-8 photoresist Silicon
AZ4620 photoresist
(g) Back side ICP (step M)
(h) Release (step N)
(i) Gold deposition (step O)
Figure 3-1. Fabrication flow (continued)
Buried oxide LPCVD nitride SU-8 photoresist Silicon Buried oxide LPCVD nitride PECVD oxide
SU-8 photoresist Silicon
Buried oxide LPCVD nitride SU-8 photoresist
Gold Silicon
Step A: RCA clean
The SOI wafer was cleaned by the standard RCA clean process before the fabrication steps. The standard RCA clean can remove organic contaminants, native oxide layer, and ionic contamination on the surface. To clean wafer completely can increase the yield rate. Note that the native oxide removal must be reduced to 30 seconds because HF etched buried oxide of the SOI wafer as well. Detailed parameters are listed below.
Step B: Front side nitride deposition
A 5000 Å thick low pressure chemical vapor deposition (LPCVD) nitride is deposited on the SOI wafer as the DRIE hard mask. The selectivity between the silicon and the LPCVD nitride in the ICP process is about 1: 70. The detailed parameters are listed below.
Description Parameters
NH3 flow rate 17 sccm
SiHCl2 flow rate 85 sccm
Process pressure 180 mTorr
Process temperature 850 °C
Deposition time 10 minutes deposition for 0.1 μm
Step Parameters
Step C: Back side oxide deposition
A 5-μm-thick oxide was deposited on the backside of the SOI wafer by plasma-enhanced chemical vapor deposition (PECVD). The process was done with an Oxford 100 PECVD Cassette System at the National Nano Device Laboratories. The deposited oxide layer was used as the hard mask during the ICP process due to its excellent selectivity. The selectivity between the oxide and the silicon in the ICP process is about 1: 100. The detailed recipes are shown below.
Step1 Step 2 Step 3 Step 4
Step D: Front side nitride patterning (Mask 1)
Mask 1 defines the device layer pattern in the 5000 Å nitride layer. FH6400 photoresist was used for the mask of nitride etching. The selectivity between silicon nitride and FH6400 photoresist is about 1: 2. So the thickness of the photoresist must be larger than 1 μm. Therefore, 2 μm thick photoresist was coated on the wafer. The photolithography process was performed by Electronic Visions EV620 double side aligner at National Tsing Hua University.
Step Description Parameters
0 Photoresist FH6400
1 HMDS coating Vapor prime oven
Coating (spread cycle) 1000 rpm 10 sec 2 Coating (spin cycle) 2000 rpm 35 sec
3 Soft bake 90 °C hotplate 150 second
4 Exposure EV620 mask aligner (9 mW/cm ) for 32 sec 2 5 Development Developer FHD-5 for 90second
6 Rinse D.I. water 1 min
7 Hard bake 120 °C hotplate 30 min
Step E: Nitride etching
After photolithography, the nitride layer was etched by SAMCO Poly-Si RIE-10N. After etching, the photoresist must be removed by ultrasonic agitation in acetone. The detailed parameters are listed below.
Description Parameters
SF6 flow rate 30 sccm
CHF3 flow rate 10 sccm
Helium backside cooling about 15 sccm
Process pressure 50 mtorr
RF power 100 W
Etch rate 10 min for 1 m nitride.
Step F: Back side oxide patterning (Mask 2)
Mask 2 defines the through-wafer holes under the push pads and the mechanical connection of the micro scanning mirror. The pattern is transferred to the back side oxide layer as the hard mask for the back side ICP process. The thick oxide layer needs a thick photoresist to mask during the etching. The selectivity between PECVD oxide and AZ4620 is about 1: 1.8, so a 9 μm thick photoresist is needed. But a 9 μm thick AZ4620 photoresist has shrinkage problems that lead to pattern offset. So a 5
μm thick AZ4620 photoresist was used this step. Therefore, step F and step G must be repeated. The detailed parameters are listed below.
Step Description Parameters
0 Photoresist AZ4620
1 HMDS coating Vapor prime oven
Coating (spread cycle) 500 rpm 10 sec 2 Coating (spin cycle) 4000 rpm 40 sec
3 Soft bake 90 °C hotplate 4.5 min
4 Exposure EV620 mask aligner (9 mW/cm2) for 13.5 sec
5 Development Developer for 3 min
6 Rinse D.I. water 5 min
7 Hard bake 120 °C hotplate 40 min
Step G: Back side oxide etching
The oxide was etched by Poly-Si RIE 10N. The etching depth in this step is 2.5 μm because the thickness of photoresist is not enough. The following is the detailed parameters.
Description Parameters
SF6 flow rate 30 sccm
CHF3 flow rate 10 sccm
Helium backside cooling about 15 sccm
Process pressure 50 mtorr
RF power 100 W
Etch rate 25 min for 2.5 m oxide.
Step H: Back side oxide patterning (Mask 2)
This step was the same as step F except for the exposure time. The exposure time was extended from 13.5 seconds to 22 seconds because the AZ4620 photoresist filled the etched patterns in step G. The thicker photoresist needs more energy for exposure.
Other conditions remained the same.
Step I: Back side oxide etching
This step was the same as step G. After etching, the photoresist was removed in acetone.
Step J: SU-8 photoresist patterning (Mask 3)
The 10-μm-thick negative photoresist SU-8 was used in this step to fabricate the fixed comb fingers. The SU-8 needs precise temperature control for pre-exposure and post-exposure bake. Hard bake is necessary for mechanical strength enhancement.
The following is the detailed parameters.
Step Description Parameters
0 Photoresist SU-8 2010
1 HMDS coating Vapor prime oven
Coating (spread cycle) 500 rpm 10 sec 2 Coating (spin cycle) 3000 rpm 30 sec 3 Pre-exposure bake 95 °C hotplate 3 min
4 Exposure EV620 mask aligner (9 mW/cm2) for 23.5 sec 5 Post-exposure bake 95 °C hotplate 3 min
5 Development SU-8 Developer for 3 min
6 Rinse IPA 10 sec
7 Hard bake 200 °C hotplate 30 min
Step K: Front side ICP etching
Inductively-coupled plasma (ICP) RIE was used in this step to etch high-aspect-ratio features in the device layer. The process etched through the 5 μm device layer to the buried oxide layer, which plays the role of etching stop. This step was performed with a STS Multiplex ICP system at Instrument Technology Research Center (ITRC). The following lists the detailed parameters.
Description Etch phase parameters Passivation phase parameters
Time per cycle 11.5 seconds 7.0 seconds
SF6 flow rate 130 sccm 0 sccm
Helium backside pressure = 10 torr Maximum helium leak up rate = 20 mtorr/min Etch rate 0.6-0.7 m per cycle depending on pattern
Step L: Wafer dicing
After the front side etching, the wafer was diced into approximate by 1cm × 1cm chips. Because the subsequent ICP etching depth is close to the entire thickness of the wafer, only diced chips are used to reduce the risk of breaking the whole wafer in the ICP chamber.
Step M: Back side ICP etching
In this step, the 400-μm-thick handle layer of the SOI wafer is etched by ICP.
The ICP system provides high aspect ratio and vertical sidewall features. Thermal release tape was used to bond the diced chip on the carrier wafer which has a 5-μm-thick oxide on it. This step etched through the 400-μm-thick substrate to the buried oxide which served as the etching stop. The parameters were the same as step K.
Step N: Release.
HF vapor was used to etch the buried oxide in order to release the structure. The experiment was shown in Figure 3-2 [39]. Temperature is critical in this step. The
surface temperature of the chip was controlled by modifying the distance between the lamp and the sample. High temperature can decrease the etching rate and low temperature can cause water condensation and stiction problems. The best distance between the lamp and the sample is about 7 cm for the range of temperature about 35-40 °C.
Figure 3-2. Schematic of the HF vapor release setup [39].
Step O: Gold deposition
After releasing the structure, the final step was to deposit gold. The gold layer was used for electrical conduction and improving the reflectivity of the mirror. The gold was deposited on the structure and the sidewall of the comb fingers. The device layer and the substrate are not shorted due to the undercut of the oxide layer in step N.
For this reason, the comb fingers are electrical isolated. Figure 3-3 shows the schematic of the gold deposition performed in an ULVAC E-Gun System at CNMM of NTHU. A 500 Å titanium layer was deposited first as the adhesion layer to avoid peeling off of the gold layer. After the Ti deposition, the 5000 Å gold was deposited.
Figure 3-3. Schematic of the gold deposition.