3-3.1.1 Id-Vg Curve
Figure 3 shows the Id-Vg curve of ZrO2 SONOS-type memory. We use channel hot electron injection (CHEI) to program and band to band hot hole to erase
(BTBHH). It is observed that after the Vg= 15V, Vd= 10V, 10 msec programming, the threshold voltage (Vth) shift from 3.75V of the fresh state to 7.35V due to electron
trapping. After Vg= -10V, Vd= 10V, 1 sec erasing, the Vth shifts leftward to 4.35V.
The memory window is 3V and this satisfies the requirement of the typical memory device – i.e. the memory window is larger than 0.7V. The electron trapping can be explained by the band diagram proposed in Fig. 4. This figure indicates the energy barrier between tunneling oxide and Si-sub is 3.1eV. When the electrons in the conduction band of silicon substrate gain enough energy from the applied voltage to across over the barrier, they can across the tunneling oxide and be trapped in the ZrO2
layer. The electron trapping causes the Id-Vg curve (in Fig. 3) after programming moving rightward and the Vth increases. Another points observed from the Id-Vg curve are that the subthreshold slope degradation of erased cell and the erased curve can’t match with the original fresh curve. The subthreshold slope degradation of
erased cell is because the BTBHH injection may damage the bottom oxide [8, 9].
There are two possible reasons why the erased curve can’t match with the original fresh curve. One is that the distribution of trapped electrons programmed by CHEI does not match with the hole by BTBHH so the injected holes during erase may not completely annihilate all of the trapped electrons leading to some negative charge left in the ZrO2 layer to result in the Vth slight increasing [9, 10]. The other reason is because that some electrons are trapped in the deep trap level of ZrO2 and hard to escape from the trapping site. This is beneficial for the memory device to retention.
3-3.1.2 Program/Erase Speed
Figure 5 shows the program speed of the ZrO2 SONOS-type memory. Figure 5 shows the program characteristics for three different stress conditions: Vg=10V, 12V, 15V and Vd=10V. The mechanism is also CHEI. The condition Vg=15V, Vd=10V, 0.1ms causes Vth shift about 2V. We can see from the figure as the applied gate voltage increases, the Vth shift also increases. This is because the larger gate voltage is applied, the more “hot” electrons are generated. There are more electrons able to cross the barrier height and trapped in the ZrO2 layer, so the Vth shift increases. The normalized erase speed curve is appeared in Fig. 6, and the same explanation can be applied on Vth shift as gate voltage becomes more negative. Using CHEI to program and BTBHH to erase can get high program/erase efficiency.
3-3.1.3 Data Retention Characteristics
The retention characteristics of ZrO2 SONOS-type memory is depicted in Fig. 7.
The retention measurement is at two temperatures of 25oC and 85oC. We find the small charge loss with time in the sol-gel ZrO2 SONOS-type memory only 5% charge loss as measure time up to 104 sec at 25oC and 20% loss at 85oC. We suggest the
contribution is from the electron deep trap of sol-gel ZrO2 charge trapping layer. The small amount charge loss at room ambient may be due to the direct tunneling current from the ZrO2 charge trapping layer to the Si-substrate or oxide trap-assisted tunneling due to the defect in the tunneling oxide.
3-3.1.4 Endurance Characteristics
Figure 8 shows the endurance of the sol-gel ZrO2 SONOS-type memory. The measure condition is program: Vg = 15V, Vd = 10V, 1 msec; erase: Vg = -10V, Vd = 10V, 10 msec. As we can see from the figure, the memory window is 2.7V. A very small increase of the erase Vth is observed. In addition, no significant window narrowing is appeared. This is due to the formation of deep trap level that makes it hard to erase all trapped electrons or misalignment of the CHEI and BTBHH distribution profile in the ZrO2 layer. After 105 P/E cycles, the memory window is still larger than 0.7 V. This finding suggests the simple sol-gel process to deposit a ZrO2
charge trapping layer can be incorporated into the SONOS-type memory fabrication.
3-3.1.5 Disturbance Measurement
Figure 9 shows drain disturbance measurement of the sol-gel ZrO2 device. We applied two stress conditions: Vd=5V and Vd=10V with Vg=Vs=Vb=0V to the device.
We can see from the Fig. 9 after 1000 sec stress the programmed state Vth loss is 0.45V for Vd=5V and 0.68V for Vd=10V.
Figure 10 shows the gate disturbance measurement of the device for two stress conditions: Vg= 10V and Vg=12V with Vd=Vs=Vb=0V. After 1000 sec stress, the fresh state Vth increases 0.1 V and 0.32V for the Vg= 10V and Vg=12V, respectively.
Figure 11 shows the read disturbance measurement of the device. The measurement conditions are fixed Vg=6V with different Vd= 3V, 4V, and 5V for 1000
sec stress. The stress caused the fresh state Vth increases 0V, 0.15V, and 0.43V for Vd= 3V, 4V, and 5V conditions respectively. We think as drain voltage increases, the more hot electrons generate and can across the energy barrier to be trapped in ZrO2 layer. This is why fresh state Vth increases.