• 沒有找到結果。

Using poly-Ge film as the channel material of TFT devices has been

implemented and the characteristics also have been demonstrated. To further enhance

the device performance, some suggestions for future work are listed below.

1. Because of the fine grain size formed by SPC method, the merits of the Ge film

are hard to stand out. In the future we suggest to replace SPC by MIC, MILC or

ELA method. By replacing the crystallization method, the process temperature

33

could even be reduced.

2. The conditions of forming raised S/D region in our study have not been optimized

yet. More efforts are needed to understand the impacts and influences of the S/D

materials on device characteristics in terms of junction properties, parasitic

resistance, as well as re-crystallization performance.

34

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42

(a)

(b) (c)

(d)

Fig. 2-1. (a) Top view layout of a raised S/D TFT device. (b) Cross-section view of a TFT device with raised poly-Si S/D. (c) Cross-section view of a TFT device with raised NiSi S/D. (d) SEM picture of a TFT device with raised NiSi S/D.

43

(a) (b)

(c) (d)

(e) (f) Fig. 2-2. Process flow of the TFT device with raised poly-Si S/D.

44

(a) (b)

(c) (d)

(e) (f)

(g)

Fig. 2-3. Process flow of the TFT device with raised NiSi S/D.

45

V

g

(V)

-8 -6 -4 -2 0 2 4

I

d

(A)

10-11 10-10 10-9 10-8 10-7 10-6

W/L = 20m/10m VD = -1V

Fig. 3-1. Transfer curves of two different poly-Ge TFT devices [30].

46

47

V

g

(V)

-16 -14 -12 -10 -8 -6 -4 -2 0 2 4

I

d

(A)

10-10 10-9 10-8 10-7 10-6

1st sweep 2nd sweep 3rd sweep 4th sweep

Vd = -1V W/L = 20m/10m

(c)

Fig. 3-2. Characteristics of drain current versus gate voltage for poly-Ge TFTs with raised poly-Si S/D showing gradually stabilized characteristics with increasing measurement sequence. (a)L=2 μm. (b)L=5 μm. (c)L=10 μm.

48

49

V

g

(V)

-16 -14 -12 -10 -8 -6 -4 -2 0 2 4

I

d

(A)

10-12 10-11 10-10 10-9 10-8 10-7 10-6

1st sweep 2nd sweep 3rd sweep 4th sweep

Vd = -1V W/L = 20m/10m

(c)

Fig. 3-3. Characteristics of drain current versus gate voltage for poly-Ge TFTs with raised NiSi S/D showing gradually stabilized characteristics with increasing measurement sequence. (a)L=2 μm. (b)L=5 μm. (c)L=10 μm.

50

Fig. 3-4. TEM cross-sectional view of poly-Ge film annealed at 500℃ for 1 hour [30].

51

Fig. 3-5. Id-Vg curves as a function of channel length for poly-Ge TFTs with (a) raised poly-Si S/D and (b) raised NiSi S/D.

52

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