The performances of our memory samples were limited by the property of the gate stack. The thick blocking oxide prevents the back injection in erase scheme but it suppresses P/E speed since the poor gate coupling. The thin tunneling oxide on poly silicon grains is suitable for P/E speed but it is not reliable for the charge retention and endurance. To optimize ONO layer is compulsory better memory performance. To adjusting the tunneling oxide and blocking oxide, high dielectric constant dielectric film, like Al2O3, can be applied as blocking oxide and also can be tried as tunneling oxide to test the immunity of roughness on poly silicon grains.
To have a better analysis of memory characteristics, the splitting of post implantation annealing time of MSB samples, which controls the S/D structure, can
implantation annealing time can be added into the split table. The trend of the change of SB-like MSB to conventional-like MSB could be modeled by the more precise and promise measure data. The program speed improvement in SB or MSB S/D TFT memory device can be further studied by analyzing the gate current of the MOSFET samples which have the same EOT with the SONOS memory samples.
There is another modified Schottky-Barrier (MSB) formation method, dopant segregation Schottky-Barrier (DSSB). As the reference [24-26], it shows well improvement on memory characteristic when the device was fabricated on silicon on insulator (SOI) substrate with multi-gate structure. The DSSB can be fabricated on TFT substrate although it would not have the advantages of low temperature or short process time. It is a good study to make a comparison between our work in this thesis and the TFT memory device with DSSB S/D.
In order to have better understanding about endurance characteristic, the samples which have done 105 P/E cycles stress are measured again 3 months later. The I-V curves of program state and erase state in the typical times of just after the 105 P/E cycles stress and 3 months after the stress are shown in Figure 4-1 for FN programming and in Figure 4-2 for CHE programming. After storing at room temperature for 3 months, samples’ swings in both program state and erase state show the recovery. It reveals that the non-uniform charge storage seems to be the main reason for swing degradation since the hard-to-erase charge is assumed to be easier to disperse than interface state. However, the Vth shift of P/E state does not follow any specific trend. Therefore, more measurements are needed to clarify the mechanisms of the degradation and recovery after P/E cycles stress.
Fig. 4-1: I-V curve of P/E state just after 105 P(FN)/E(FN) cycles and 3 months later.
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簡歷
姓名: 賴瑞堯
性別: 男
出生年月日: 西元 1985 年 1 月 31 日
出生地: 台灣 彰化縣
學歷:
國立科學工業園區實驗高級中學 (2000.9 ~ 2003.6)
國立交通大學電子工程學系學士 (2003.9 ~ 2007.6)
國立交通大學電子研究所碩士 (2007.9 ~ 2010.6)
碩士論文:
修正蕭基位障非揮發性記憶體於薄膜電晶體基板之研究
A Study on Non-volatile Memory with Modified Schottky Barrier S/D on TFT Substrate