In this work, it has been demonstrated that the overshoot current during the forming/set operation influences the electrical characteristics significantly, and the external 1T1R fails in eliminating the issue. To make the effects of overshoot current negligible, compliance current larger than 0.1mA is used in this work. However, one of the attractive features of RRAM for the next generation memory is its ability to switch with low operation power. Thus it’s important to investigate the electrical characteristics with lower compliance current. To accomplish this goal, the integrated 1T1R configuration in which the RRAM cell connected to the drain side of the transistor must be used. It should be mentioned that the transistor in the 1T1R configuration is best to have drive current and on/off ratio as large as possible, because that the RRAM cell and the transistor are connected in series during device fabrication. During reset operation, the gate voltage should be larger than that during forming/set operation for the RRAM cell to reach the reset current. With larger drive current and on/off ratio, it is more flexible for choosing appropriate compliance current.
The RRAM cells fabricated in this work show significant cell-to-cell variation, together with the effect of overshoot current, it is in fact very difficult to observe some clear tendencies between the process conditions and electrical characteristics.
As has been reported previously [58], downscaling the cell area may improve the
29
variation issue due to the reduction of defects in the cell. Smaller cell area offers additional advantages such as a higher HRS resistance and more efficient local heating effect because of a reduced number of conductive filaments. The compliance current can also be lowered with a smaller cell area because of a lower leakage current of the fresh RRAM cell. Summing up the advantages mentioned above, it is suggested to fabricate RRAM cells with an area much less than that of the devices characterized in this study in the future.
30
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36
Fig. 1-1 Sketch of a crossbar array [42].
Fig. 1-2 C–V curves under reverse bias for a Ti/PCMO/SRO cell, indicating that the depletion layer width (Wd) at the Ti/PCMO interface is altered by applying an electric field [11].
37
Fig. 1-3 Schematic sketch of conductive filament model [11].
Fig. 1-4 Schematic sketch of possible filament forming process with a Ti buffer layer, indicating that the filament formation is easier in the oxygen deficient region [28].
38
Fig. 1-5 Difference between memory switching and threshold switching [32].
Fig. 1-6 Sketch of field induced barrier lowering in Poole-Frenkel model.
39
Fig. 1-7 Different current behavior regions for insulators with deep traps and shallow traps, respectively.
40
Fig. 2-1 A sketch of fabricated cells with all of the films except SiO2 deposited by using reactive sputtering method.
Fig. 2-2 Output characteristics of the transistor used in the external 1T-1R configuration, the channel length and width are both 100 um.
41
Fig. 2-3 Unipolar and bipolar switching schemes. CC denotes the compliance current which is often needed to limit the ON current [15].
42
Fig. 3-1 Switching characteristics of a Ni/HfOx(50nm)/TiN RRAM cell.
Fig. 3-2 Resistances of the high-resistance state and low-resistance state (LRS/HRS) measured during the successive 100 cycles.
43
Fig. 3-3 The relationship between the LRS resistance and the compliance current of Ni/HfOx(40nm)/TiN RRAM cell. Also shown in the figure is the standard deviation of the LRS resistance.
Fig. 3-4 The relationship between the compliance current and the reset current.
44
Fig. 3-5 The cumulative probability of HRS resistances of Ni/HfOx(40nm)/TiN RRAM cells with various compliance current. (C.C.: Compliance current).
45
Fig. 3-6 (a) The cumulative probability of HRS resistances with various Vrs.
(b) The cumulative probability of HRS resistances with different HfOx thickness and Vrs of 1 volt.
46
47
Fig. 3-7 (a) Forming voltage versus oxide thickness. (b) Set voltage versus oxide thickness. (c) Set voltage as a function of Vrs for cells with HfOx of 40 nm.
48
Fig. 3-8 The bipolar switching characteristics of a TiN/Ti/HfOx/TiN cell with compliance current 0.1m A.
Fig. 3-9 The switching behaviors of TiN/Ti/HfOx(20nm)/TiN RRAM cell with different compliance current.
49
Fig. 3-10 The HRS/LRS resistances during successive 100 cycles, in which the compliance current was modified in cycle 4 and cycle 33.
Fig. 3-11 The relationship between the forming voltage and the reset current during the first reset process.
50
Fig. 3-12 A schematic diagram for understanding the different overshoot currents caused by different forming voltage [52].
51
Fig. 3-13 (a) The switching characteristics of a TiN/Ti/HfOx(20nm)/TiN RRAM cell with forming voltage of approximately 4 V.(b) The switching characteristics of a TiN/Ti/HfOx(20nm)/TiN RRAM cell with forming voltage of approximately 1.5 V.
(a)
(b)
52
Fig. 3-14 (a) The characteristics of TiN/Ti/HfOx(10nm)/TiN RRAM cells with various thickness of Ti buffer layer. (b) The characteristics of
TiN/Ti/HfOx(20nm)/TiN RRAM cells with various thickness of Ti buffer layer.
(a)
(b)
53
Fig. 3-15 The switching characteristics of a Ni/HfOx(40nm)/TiN RRAM cell measured with the external 1T1R configuration.
54
Fig. 3-16 (a) I-V characteristics of a fresh Ni/HfOx(20nm)/TiN RRAM cell. (b) I-V characteristics of a fresh TiN/Ti/HfOx(20nm)/TiN RRAM cell.
(b)
(a)
55
Fig. 3-17 (a) I-V characteristics of a Ni/HfOx(20nm)/TiN RRAM cell in HRS. (b) I-V characteristics of a Ni/HfOx(20nm)/TiN RRAM cell in LRS.
(b)
(a)
56
Fig. 3-18 (a) I-V characteristics of Ni/HfOx(20nm)/TiN RRAM cell in LRS. (b) I-V characteristics of Ni/HfOx(20nm)/TiN RRAM cell in HRS, which can be fitted using Poole-Frenkel model.
(b)
(a)
57
Fig. 3-19 (a) I-V characteristics of TiN/Ti/HfOx(20nm)/TiN RRAM cell in LRS. (b) I-V characteristics of TiN/Ti/HfOx(20nm)/TiN RRAM cell in HRS.
(b)
(a)
58
Fig. 3-20 (a) The temperature dependence of both HRS resistance and LRS resistance of a Ni/HfOx(20nm)/TiN RRAM cell. (b) The temperature dependence of both HRS resistance and LRS resistance of a TiN/Ti/HfOx(20nm)/TiN RRAM cell.
(b)
(a)
59
Fig. 3-21 The I-V curve of a Ni/HfOx(20nm)/TiN RRAM cell in LRS, also shown in the figure is the local temperature of the conductive filament calculated using the extractedα value and the continuously changing resistance before the cell reaches reset voltage.
60
Fig. 3-22 The temperature dependence of LRS resistance for a Ni/HfOx(20nm)/TiN RRAM cell.
61
Fig. 3-23 The extracted activation energies form the ln(I/V) versus 1/kT plot for different biases.
Fig. 3-24 The relationship between extracted activation energy and the applied bias.
62
Vita
姓名：王佳文
性別：男
生日：78.7.29
出生地：台南市
籍貫：台灣省 台南市
地址：台南市安南區安中路一段 936 號
學歷：
台南市國立台南一中 2004.09~2007.06
國立中山大學 物理學系 2007.09~2011.06
國立交通大學 電子工程研究所 2011.09~2013.07
論文題目：以氧化鉿為介電層的電阻式隨機存取記憶體之電性探討與分析
Electrical Characteristics and Analyses of HfOx-Based Resistive Random Access Memories