Fig. 4-1 shows the extracted work function versus rapid thermal anneal temperature. The
work function of Mo-silicided gate after 600 ℃ and 700 ℃ is about 4.813 eV and 4.792 eV,
respectively. The work function of gate electrode have only a negligible variation. After 800
℃ rapid thermal anneal, The work function of Mo-silicide shift to 4.34 eV. This situation is
quite similar to using Mo-silicided gate electrode with SiO2 gate dielectric, and has not seen
obvious fermi pinning effect. This may be due to fermi pinning level very close to 4.34 eV.
Fig. 4-2 shows the variation of equivalent oxide thickness of FUSI molybdenum silicide gated
MOS capacitors on HfO2 versus different temperatures. Excellent thermal stability up to 950
℃ is observed. The Mo-silicided gate is quite stable on hafnium dioxide.
The work function of undoped Mo-silicide gate electrode on HfO2 is about 4.34 eV. That
is just suitable for FinFET and ultra-thin body (UTB) MOSFET device. Therefore, we use As
ion implantation to dope the gate electrode and observe the change of work function.
Silicidation was performed under the same FUSI condition in chapter 3 for 5x1015 cm-2
As-doped samples. The extracted work function values are summarized in Fig. 4-3 after 800
℃ RTA. Comparing the work function of doped and undoped Mo-silicide, it becomes evident
that the arsenic dopants strongly affect the work function of formed Mo-silicides. That may be
attributed to the As pile-up at the Mo-silicide and HfO2 dielectric interface changing the
electrical property of MOS capacitor. The work function difference between As-doped and
undoped Mo-silicide with HfO2 gate dielectric can be at least up to 0.363 eV, and the work
function of Mo-silicided gate with As 5x1015 cm-2 on HfO2 dielectric becomes 4.16 eV, that is
suitable for bulk nMOSFET device.
The thermal stability of Mo-silicide gate with 5x1015 cm-2 As-implant is further
investigated by RTA up to 950 ℃. The equivalent oxide thickness of Mo-silicide gated MOS
capacitors with 5x1015 cm-2 As-implant on HfO2 shows negligible change even after annealing
at 950 ℃, as shown in Fig. 4-4.
Based on these results, Mo-silicide gate with 5x1015 cm-2 As implanted on HfO2 gate
dielectric during 800 ℃ 30s RTA may chose for bulk nMOSFET device fabrication.
pMOSFET device with HfO2 gate dielectric also fabricated and discussed. The work
function of pure Molybdenum gate with HfO2 gate dielectric after 950 ℃ rapid thermal
anneal is about 4.906 eV. The C-V curve of pure Molybdenum gated MOS capacitor with
HfO2 gate dielectric was shows in Fig. 4-5, and Fig. 4-6 shows the oxide quality leakage
current characteristic. The leakage current of MOS capacitor with high-k HfO2 dielectric is
smaller than that of MOS capacitor with SiO2 gate dielectric. Using HfO2 as gate oxide can
make the gate oxide leakage current improve about 2 orders than SiO2. Therefore, pure Mo
gated MOSFET device with HfO2 gate dielectric may chose for pMOSFET device fabrication.
We proposed and demonstrated fully silicided Mo-silicide with 5x1015 cm-2 As implanted
as a metal-gate material for nMOSFETs (work function 4.16 eV) and pure Mo as a metal-gate
material for pMOSFETs (work function 4.906 eV) on HfO2 high-k gate dielectric, those were
compatible with CMOS processing. Negligible change in flat-band voltage and equivalent
oxide thickness are observed even after annealed at 950 ℃, demonstrating its excellent
thermal stability. The gate oxide leakage current of CMOS device can also get suitable
improvement than SiO2. Therefore, Mo-silicide for nMOSFET with pure Mo for pMOSFET
is the promising candidate for dual-metal CMOS process with HfO2 High-k dielectric.
Chapter 5
Conclusion
This thesis investigated the work function adjustability of fully Mo-silicide films and the
thermal stability of gate dielectric and equivalent oxide thickness of Mo-silicide MOS devices.
The molybdenum and amorphous silicon were deposited by sputtering system in Ar ambient.
Samples with metal/SiO2/Si-sub MOS structures annealed at different temperature in RTA
(rapid thermal anneal) system in N2 ambient were used to analyze the thermal stability of the
flat-band voltage and equivalent oxide thickness. Using the same process condition, the
molybdenum and amorphous silicon were deposited on HfO2 high-k Dielectric that deposited
by MOCVD system. Investigating the work function adjustability and thermal stability of
flat-band voltage and equivalent oxide thickness of MoSix/High-k/Si-sub structures.
The work function of the Molybdenum silicide on SiO2 dielectric decreased from 4.78
eV to 4.39 eV as anneal temperature increased to 800 30s. And on the aspect of the ℃
molybdenum silicidation on HfO2 high-k dielectric, the work function was decrease from 4.81
eV to 4.34 eV as anneal temperature increase to 800 30s. The work function of the ℃
molybdenum silicide has not seen obvious fermi pinning effect. This may be due to fermi
pinning level very close to 4.34 eV. After that, using arsenic ion implantation to add arsenic to
gate of MOS structure, to cause the work function of the gate on SiO2 dielectric decrease to
4.001 eV. And the work function of the gate on HfO2 high-k dielectric decrease to 4.16 eV.
To investigate the thermal stability of gate oxide and equivalent oxide thickness, the
samples were annealed by RTA system at 600 ℃、700 ℃、800 and 950 , and found that ℃ ℃
no matter what metal silicide on SiO2 or HfO2 dielectric, the deviation of the metal work
function and equivalent oxide thickness annealed among 800 and 950 can be neglect. ℃ ℃
Suggesting the molybdenum silicide metal gate can replace the traditional n+ poly-Si gate.
The work function of pure Mo on SiO2 and HfO2 is about 4.931 eV and 4.906 eV,
respectively. That is very close to the valance band of silicon. The deviation of the metal work
function and equivalent oxide thickness annealed up to 950 can be neglect. ℃
Based on these results, Mo-silicide gate for nMOS and pure Mo gate for pMOS may
chose for CMOS device fabrication.
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Near Ec Mid Gap Near Ev
Nb 3.9~4.3 Co 4.41~5.00 Pt 5.32~5.50
Al 4.06~4.20 W 4.10~5.20 RuO2 4.90~5.20
Ta 4.12~4.60 Ru 4.60~4.71 TiN 4.70~4.90
Zr 3.9~4.05 Au 4.52~4.77 MoNx 5.33
Ti 3.95~4.33 Pd 4.80~5.22 WNx 5
TaN 3.90~4.20 Ni 4.50~5.30 Mo 4.60~4.90
Table 1-1 The work function of some metals reported in literatures.
Near Ec Mid Gap Near Ev
Nb 15 Co 6.86 Pt 10.5 Al 2.65 W 5.48 RuO2
Ta 13 Ru 7.1 TiN >100
Zr 42 Au 2.4 MoNx >100
Ti 40 Pd 10 WNx >100
TaN 225 Ni 6.9 Mo 4.76
Poly-Si(As) >1000 Poly-Si(B) >1000
Table 1-2 The risistivity (µΩ-cm) of some metals reported in literatures.
Near Ec Mid Gap Near Ev
Nb 2468 Co 1490 Pt 1755
Al 660 W 3370 RuO2 1200
Ta 2996 Ru 2250 TiN 3290 Zr 1852 Au 1063 MoN 1750
Ti 1660 Pd 1552 WNx
TaN 3090 Ni 1453 Mo 2890
Table 1-3 melting point (°C) of some metals reported in literatures.
Process step Condition
1.Isolation Fox=550 nm
2.SiO2 formation 3nm, 6nm, 7nm
3.Mo and Si deposition by sputtering Thickness of Mo 10nm
Thickness of Si 25nm
Vacuum pressure 2x10-6 torr Process pressure 7.6x10-6 torr DC power 150 W
Gas Ar 24 sccm 4.Electrode pattering Area 100µm x100µm
5.Rapid Thermal Anneal 600~950℃ 30s in N2 ambient
Table 2-1 The process flow chart of molybdenum silicided gate capacitor with SiO2
dilectric.
Process step Condition
1.Isolation Fox=550 nm
2.HfO2 formation 5nm, 7.5nm, 10nm
3.Mo and Si deposition by sputtering Thickness of Mo 10nm
Thickness of Si 25nm
Vacuum pressure 2x10-6 torr Process pressure 7.6x10-6 torr DC power 150 W
Gas Ar 24 sccm 4.Electrode pattering Area 100µm x100µm
5.Rapid Thermal Anneal 600~950℃ 30s in N2 ambient
Table 2-2 The process flow chart of molybdenum silicided gate capacitor with HfO2
dilectric.
Fig. 1-1 Boron penetration through the gate oxide cause the threshold voltage in BF2-impaaented p-channel devices to shift positive at anneal temperature above ~800 ℃
Fig. 1-2 Threshold voltage versus work function of gate electrode for both nMOSFET and pMOSFET with different surface concentration.
Vacuum
Ec
Ev
qχ+ Eg
=5.17eV
Eg
=1.12eV
qχ = 4.05eV
Ei
Fig. 1-3 Band diagram of silicon conduction and valence band.
Fig. 1-4 Using a single gate material for both nMOS and pMOS devices can yield symmetric but large threshold voltages. Achieving low and symmetric threshold voltages will require two different mid-gap gate materials.
Fig. 1-5 Schematic energy band diagram for a metal gate on a dielectric, showing extrinsic states that pin the metal Fermi level. The energy level of the extrinsic states, i.e., pinning level, could be related to the interfacial bonding defects between the metal and the dielectric. The conduction-band edge and the valence-band edge of the dielectric are denoted by Ec,d and Ev,d respectively.
Fig. 1-6 Cross sections illustrating the dual-metal gate process, after etching TiN/Ti and before deposition of Mo and TiN (top), and after the gate etch and source-drain implantation to show the gate stack (bottom).
Fig. 1-7 Schematic illustration of the process flow. (a) CMOS structure after second metal has been removed from the nMOS side. (b) CMOS structure after annealing shows that the metals on the pMOS side have interdiffused, and second metal has segregated to the dielectric interface.
Fig. 1-8 XPS depth profile for Ti/Ni gate electrode after the 400 ℃, 30 min interdiffusion anneal. A large concentration of Ni is present at the SiO2 interface.
(a) (c)
(b) (d)
Fig. 1-9 Fully silicide heavily implanted poly-Si gate electrode.(a)traditional poly-Si gate formation(b)B, P, As implant in poly-Si(c)metal deposition(d)silicidation by high temperature annealing.
(a) (f)
(b) (g)
(c) (h)
(d) (i)
(e)
Fig. 1-10 The schematic of CMOS device process flow diagram. Using molybdenum silicided gate and pure molybdenum gate for nMOSFET and pMOSFET, respectively.
Fig. 3-1 C-V curves for pMOS capacitors with different thickness of α-silicon layer after 800 ℃ RTA.
Fig. 3-2 Flat-band voltage as a function of the equivalent oxide thickness. A larger flat-band voltage variation is observed between 700 ℃ and 800 ℃ RTA (work function:
4.796 eV for 700 C RTA and 4.389 eV for 800 ℃ RTA).
Fig. 3-3 Extracted Work function versus the RTA temperature. After 800 ℃ RTA, evidence of silicidation is observed by the change of work function.
Fig. 3-4 Dependence of sheet resistance of Mo/α-Si stack layers on annealing temperatures.
Fig. 3-5 Variation of equivalent oxide thickness of molybdenum silicide gated MOS capacitors with annealing temperature. Excellent thermal stability up to 950 ℃ can be observed.
Fig. 3-6 No degradation in gate leakage current is found after high-temperature annealing.
Fig. 3-7 Hysteresis of Mo-silicide gated MOS capacitor after 950 ℃ rapid thermal anneal still exhibits negligible.
Fig. 3-8 Flat-band voltage versus the equivalent oxide thickness with As-doped and undoped Mo-silicide gate (work function: 4.389 eV for undoped and 4.202 eV for As 1x1015 cm-2 dosage, 4.01 eV for As 5x1015 cm-2 dosage).
Fig. 3-9 The work function of Mo-silicided gate vs. As implanted dosage.
Fig. 3-10 Variation of equivalent oxide thickness of molybdenum silicide gated MOS capacitors with annealing temperature. Excellent thermal stability up to 950 ℃ can be observed.
Fig. 3-11 Flat-band voltage of pure Mo gated MOS capacitor versus the equivalent oxide thickness.
Fig. 3-12 Hysteresis of pure Mo gated MOS capacitor with 950 ℃ rapid thermal anneal still exhibits negligible.
Fig. 4-1 Extracted work function versus RTA temperature.
Fig. 4-2 Variation of equivalent oxide thickness of molybdenum silicide gated MOS capacitors on high-k HfO2 verse annealing temperatures. Excellent thermal stability up to 950 ℃ can be observed.
Fig. 4-3 The work function of Mo-silicided gate on HfO2 dielectric versus As implanted dosage after 800 ℃ RTA.
Fig. 4-4 Variation of equivalent oxide thickness of molybdenum silicide gated MOS capacitor with As 5x1015 cm-2 dosage on HfO2 annealing at different temperatures.
Excellent thermal stability up to 950 ℃ can be observed.
Fig. 4-5 The C-V curve of pure Molybdenum gated MOS capacitor undergo 950 ℃ RTA.
Fig. 4-6 Oxide quality leakage current characteristic.