In this work, channel material quality and the device structure are not optimized,
and the leakage current is rather high. It has been found that polycrystalline
silicon-germanium film has much more defects than polycrystalline silicon film. To
further improve the device performance, it is important to reduce the defects and
trap-states in silicon-germanium film for the nanowire TFTs. It could be achieved by
using laser annealing, MILC, SPE or other new technologies replacing the SPC step
to enlarge the grain size of the silicon-germanium film, or we can use other plasma
treatment technology to aid NH3 plasma treatment.
Although double-gated nanowire TFTs have been demonstrated to show better
device performance, further improvement in the electrical performance is possible by
adding a back-gate to form a tri-gated nanowire TFTs, or by modifying the structure
to form a surrounding-gate nanowire TFTs. As long as decent performance is achieved,
the new nanowire device can be readily applied to a variety of novel applications in
the future.
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Table 2-1 NH3 plasma treatment conditions.
Plasma RF power (watt)
Pressure (pa)
Flow rate (sccm)
Temperature (℃)
NH3 200 50 200 300
Table 3-1 Key parameters of the silicon-germanium nanowire TFTs with different NH3 plasma passivation times.
NH3 plasma passivaiton
time
Threshold Voltage (V) Vth
Subthreshold swing (V/decade)
S.S.
mobility
As-fabricated 12.96 1.36 0.87
30 mins 7.00 0.705 5.62
1 hour 5.75 0.572 11.87
Table 3-2 Summary of key parameters for n-type poly-Si and poly-Sil-xGex nanowire TFTs at VD = 0.5 V.
Table 3-3 Summary of key parameters for p-type poly-Si and poly-Sil-xGex nanowire TFTs at VD = 0.5 V.
SiGe-channel 3.74 0.77 12.03
P-Channel
SiGe-channel -12.3081 0.87 4.40
Table 4-1 Characteristics of nanowire TFT with DG and SG operations.
Table 4-2 Improving DIBL effect by varying sub-gate voltage.＼
Threshold voltage
Figure 2-1 Definition of the main gate.
Figure 2-2 Deposition of LPCVD TEOS and channel layer.
Figure 2-3 Ion implantation.
Figure 2-4 Self-aligned formation of nanowire channel.
Figure 2-5 Deposition of passivation oxide layer.
Figure 2-6 Definition of sub-gate.
Figure 2-7 Top view of nanowire TFT with double-gated structure.
Figure 2-8(a) Cross sectional picture of sidewall spacer nanowire channel of poly-Si TFT.
Figure 2-8(b) Cross sectional picture of sidewall spacer nanowire channel of poly-Si TFT.
Figure 2-8(c) Cross sectional picture of sidewall spacer nanowire channel of poly-SiGe TFT.
VD = 0.5 V, L = 1 µm
Figure 3-1 Transfer characteristics of silicon-germanium nanowire TFTs with different NH3 plasma passivation times.