When the channel length reduces, our NWs still possess good gate control abilities. Therefore, if we can design a layout with increased NW count in a unit area to provide sufficient current drive, it is believed that NW-TFTs will become a promising candidate for future applications.
The fabricated S3 device is a GAA NW, but its shape is not preferred for electrical characteristics because of the sharp corners. Hence we have to improve the NW structure and make it close to a circle, which is suitable for the applications of both MOS-type and SONOS-type devices. Besides, we should deposit thinner
blocking oxide for our SONOS devices to reduce the operation voltage and/or to increase the P/E speed.
. In this study, we have demonstrated many important and interesting results about NW characteristics. Nevertheless, it is a pity that we don’t have a complete model to explain the characteristics of the NW devices. Therefore, performing more simulation work to justify our findings is another urgent work in the future.
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Gate
Fig. 2-1 Key steps of NW devices fabrication (a) Top-view of the NW device. (b) Nitride and TEOS formed on Si-substrate capped with a buried oxide. (c) Nitride patterned by anisotropic reactive plasma etching. (d) Undercut formed by isotropic DHF wet etching.
(e) a-Si deposition and annealing, and S/D implant. (f-1) Si removal with anisotropic dry etching. (f-2) Nitride removal with hot H3PO4. (f-3) Portion of TEOS removed by DHF.
(g-1 to g-3) gate oxide and poly gate deposition.