In this thesis, electrical characteristics of planar DG-TFTs have been developed and characterized. For the purpose of further improvement, some topics and directions for the future work are suggested as follows:
1. From the output characteristics, it could be seen that the carrier transport at the top and bottom channel is poor due to the grain boundaries. In this thesis, poly-Si TFTs were prepared by solid-phase crystallization (SPC). However, many methods are known to increase the grain size of the poly-Si thin film, such as excimer laser annealing (ELA) and metal-induced lateral crystallization (MILC).
DG-TFTs with large-grain-poly-Si channel are expected to exhibit much improved performance and interesting characteristics under the DG mode of operation.
2. In order to further improve performance, ultra-thin body (Tsi<10nm) is needed to eliminate any leakage paths and to enhance the gate coupling effect. However, the high parasitic resistance due to the ultra-thin body needs to be addressed in the device fabrication.
3. In this thesis, due to the time limitation, we only focus on the study of NW-TFTs fluctuation. Of course the issue also exists in the planar-TFTs, and deserves to be
thoroughly addressed.
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Si Substrate Bottom Gate
Body Top Gate
S D
TEOS
Si Substrate Bottom Gate
Body Top Gate
S D
TEOS
Fig. 2-1 The structure of DG-TFTs
Si Substrate Bottom Gate Si Substrate Bottom Gate
Fig. 2-2 (a) Deposition of in-situ doped n+ poly-Si bottom gate and bottom gate oxide.
Si Substrate Bottom Gate
Body
Si Substrate Bottom Gate
Body
Fig. 2-2 (b) Deposition and pattern of poly-Si body.
Si Substrate Bottom Gate
Top Gate
TEOS Body
Top Gate
Si Substrate Bottom Gate
Top Gate
TEOS Body
Top Gate
Fig. 2-2 (c) Deposition of 20nm-thick top gate oxide and 100nm poly-Si top gate.
Si Substrate Bottom Gate
Body Top Gate
S D
TEOS
Si Substrate Bottom Gate
Body Top Gate
S D
TEOS
Fig. 2-2 (d) Definition of poly-Si top gate and self-aligned implantation.
Fig. 2-3 Top view and cross-sectional view of inverse-T double-gate NWTFTs.
Si Substrate Thermal Oxide
Si Substrate Si Substrate Thermal Oxide Thermal Oxide
Fig. 2-4 (a) Deposition of in-situ doped n+ poly-Si on glass like substrate.
Si Substrate Thermal Oxide
Si Substrate Si Substrate Thermal Oxide Thermal Oxide
Fig. 2-4 (b) Definition of inverse-T gate.
Si Substrate Thermal Oxide
Si Substrate Si Substrate Thermal Oxide Thermal Oxide
Fig. 2-4 (c) Deposition of inverse-T gate oxide and poly-Si active layer.
Si Substrate Thermal Oxide
Si Substrate Si Substrate Thermal Oxide Thermal Oxide
Fig. 2-4 (d) Source/drain ion implantation.
Si Substrate Thermal Oxide
Drain
Gate Source
Poly-Si NW Channel
Si Substrate Thermal Oxide
Si Substrate Si Substrate Thermal Oxide Thermal Oxide
Drain
Gate Source
Poly-Si NW Channel
Drain
Gate Source
Poly-Si NW Channel
Fig. 2-4 (e) Definition of source/drain and nanowire channel.
Si Substrate Thermal Oxide Drain
Gate Source
Poly-Si NW Channel
Gate
Si Substrate Si Substrate Thermal Oxide Thermal Oxide Drain
Gate Source
Poly-Si NW Channel
Gate
Drain
Gate Source
Poly-Si NW Channel
Gate
Fig. 2-4 (f) Formation of top gate.
Vg (V)
Fig. 3-1 Transfer characteristics of DG-TFTs under different operation modes: (a) before NH3-plasma treatment, and (b) after NH3-plasma treatment.
Vg (V)
Fig. 3-2 Transfer characteristics of a short-channel (L=0.7μm) device under TG and DG modes of operation.
Vg (V)
Fig. 3-3 Transfer characteristics of a DG-TFT under different operation modes. The channel thickness is 50nm. Bottom and top gate oxide are both 20nm.
Vg (V)
Fig. 3-4 Transfer characteristics of devices with asymmetric gate oxide and channel thickness of (a) 30nm and (b) 50nm. Bottom and top gate oxide are 50nm and 20nm, respectively.
Vd (V)
Fig. 3-5 Output characteristics of a device with symmetric gate oxide of 20nm and channel thickness of 30nm.
Vg (V)
Fig. 3-6 Mobility of a device under different modes of operation. The device is with symmetric gate oxide of 20nm and channel thickness of 30nm.
Gate
SiO2 SiO2
Body Gate Gate
SiO2 SiO2
Body Gate
(a)
Gate
SiO2 SiO2
Gate Gate Body
SiO2 SiO2
Gate Body
(b)
Fig. 3-7 Energy band diagrams for (a) thick channel body, (b) thin channel body.
Dashed lines represent the distribution of the inversion charges.
Fig. 3-8 Simulated electron wave functions in the channel of a DG configuration under different Si channel thickness and bias conditions.[13]
Vd (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Drain current ratio IDG/(ITG+IBG)
0.5
Fig. 3-9 Drain current ratio for the results shown in Fig. 3-5.
Channel Lenght (μm)
Channel Length (um)
Fig. 3-10 The series resistance of devices under (a) TG, (b) BG, and (c) DG operation modes. The devices are with symmetric gate oxide of 20nm and channel thickness of 30nm.
Vg (V)
Fig. 3-11 Transconductance of a device under different operation modes. The device is with symmetric gate oxide of 20nm and channel thickness of 30nm.
Vd (V)
Vd (V)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Drain current ratio IDG/(
I TG
Drain current ratio IDG/(
I TG
Fig. 3-12 (a) Output characteristics of a device with symmetric gate oxide of 20nm and channel thickness of 50nm. (b) The extracted drain current ratio.
Top gate Voltage (V)
-2 0 2 4 6
Fig. 3-13 Modulation of transfer characteristics with BG voltage.
BG Voltage (V)
BG Depletion BG Inversion
ΔVTH=0.32V/V
BG Depletion BG Inversion
ΔVTH=0.32V/V
ΔVTH=2.84V/V
Fig. 3-14 Modulation of Vth (TG) and SS as a function of BG voltage.
Fig. 3-15 Schematic illustration of the potential variation with various bias configurations. [15]
Top gate voltage (V)
Top gate voltage (V)
-4 -2 0 2 4 6 8
Fig. 3-16 Modulation of transfer characteristics with BG voltage for a device with symmetrical gate oxide (20nm). The channel thickness is 50nm.
Top gate voltage(V)
Fig. 3-17 Modulation of transfer characteristics with BG voltage for a device with asymmetrical gate oxide. The channel thickness is 30nm.
BG Voltage (V)
BG Depletion BG Inversion
BG Voltage (V)
BG Depletion BG Inversion
BG Voltage (V)
BG Depletion BG Inversion
Fig. 3-18 Modulation of Vth (TG) and SS as a function of BG voltage for devices with symmetrical and asymmetrical gate oxide configurations.
Fig. 3-19 Schematic Id–Vg curves of a DG modulated by a control gate for active- and standby-state operation [41].
50nm
80nm 40nm
50nm
80nm 40nm
50nm
80nm 40nm
(a)
200 nm Inverse
-T gate NW
channel 45nm
30nm
20nm Top gate
(b)
Fig. 4-1 Cross-sectional TEM views of NW-TFTs: (a) NW-A type and (b) NW-B type.
-1 0 1 2 3 4 5
Fig. 4-2 Transfer characteristics of NW-A devices with (a) L=0.8μm, (b) L=2μm, and (c) L=5μm.
In each split 25 devices were measured.
VTH (V)
0.25 0.30 0.35 0.40 0.45 0.50 0.55
Counts
Fig. 4-3 (a) Distribution, (b) mean-value and standard deviation of VTH of NW-A devices with various channel length.
-1 0 1 2 3 4 5
Fig.4-4 Transfer characteristics of NW-B devices with (a) L=0.8μm, (b) L=2μm, and (c) L=5μm. In each split 25 devices were measured. (d) Mean-value and standard deviation of VTH of the NW-B devices with various channel length.
Fig. 4-5 Schematic illustration of electric field, E, as a function of depth x in the channel region of an MOSFET [31].
gate dielectric
Fig. 4-6 VTH dependence on the poly-Si channel thickness: (a) single-gated devices with partially depleted channel, (b) single-gated devices with fully depleted channel, and (c) double-gated devices with fully depleted channel.
Trap
1/(LW)1/2 (μm-1)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VTH Standard Deviation (mV) 0 10 20 30 40 50
NW-B NW-A
Y=24X
Y=15X
Fig.4-7 VTH standard deviation of the NW-A and NW-B devices as a function of 1 LW .
(W /LW)d 1/2 (nm1/2-μm-1)
0 1 2 3 4 5 6 7
VTH Standard Deviation (mV) 0 10 20 30 40 50
NW-B NW-A
WDEP:
NW-B = 4nm NW-A = 12nm
Fig. 4-8 VTH standard deviation of NW-A and NW-B devices as a function of Wd LW .
L=0.8um L=2um L=5um
Fig. 4-9 Mean value and standard deviation of VTH of NW-A devices (a) before and (b) after NH3-plasma treatment.
-1 0 1 2 3 4 5
Fig. 4-10 Transfer curves of NW-A devices (a) before and (b) after NH3-plasma treatment.
NT1/2
(cm-3/2)
0.0 1.0e+9 2.0e+9 3.0e+9 4.0e+9 5.0e+9 VTHSddDii
VTH Standard Deviation (mV) 0
VTH Standard Deviation (mV) 0
VTH Standard Deviation (mV) 0 Ttrap for treatment=1.6X1012 cm-2
NW-A
(Ttrap/LW)1/2 (μm-1)
0 100 200 300 400 500
VTH Standard Deviation (mV) 0 Ttrap for treatment=1.6X1012 cm-2
NW-A
(b)
Fig. 4-12 VTH standard deviation of NW-A devices before and after NH3-plasma treatment.
1/(LW)1/2 (μm-1)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VTH Standard Deviation (mV) 0
VTH Standard Deviation (mV) 0 VTH Standard Deviation (mV)
0 VTH Standard Deviation (mV)
0
Fig. 4-13 VTH standard deviation of NW-B devices before and after NH3-plasma treatment.
(WdNtrap/LW)1/2 (nm-μm)-1
0.00 0.05 0.10 0.15 0.20 0.25 0.30 VTH Standard Deviation (mV)
0
Fig. 4-14 VTH standard deviation of NW-A and NW-B devices as a function of.
LW N Wd T
.
1/(LW)1/2 (μm-1)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VTH Standard Deviation (mV) 0
Fig. 4-15 VTH standard deviation of NW-A devices under various operation modes as a function of 1
Fig. 4-16 Transfer curves of NW-A devices in (a) ITG mode; (b) TG mode. In each figure 25 devices were measured. Three different voltages (-1, 0, and 1V) were applied to the control gate to modulate the transfer characteristics.
TG voltage (V)
-1V 0V 1V
VTH Standard Deviation (mV) 0
VTH Standard Deviation (mV) 0
VTH Standard Deviation (mV) 0
VTH Standard Deviation (mV) 0
Fig. 4-18 Distribution of transfer curves in ITG mode.
1/(LW)1/2 (μm-1)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VTH Standard Deviation (mV) 0 10 20 30 40 50 60 70 80 90 100 110
ITG voltage=-1V ITG voltage=0V ITG voltage=1V DG mode
TG mode, VD = 0.5V Tox = 20nm
Figure 4-19 Standard deviation of VTH for TG and DG modes.
Table 3-1. Subthreshold slope for DG-TFTs (at VD=0.5V) under various operation modes.
TG mode BG mode DG mode
DG1 Tsi=30nm Tox,top=20nm Tox, bottom=20nm
554 (mV/dec) 690 (mV/dec) 422 (mV/dec)
DG2 Tsi=50nm Tox,top=20nm Tox, bottom=20nm
480 (mV/dec) 620 (mV/dec) 430 (mV/dec)
DG3 Tsi=30nm Tox,top=20nm Tox, bottom=50nm
560 (mV/dec) 750 (mV/dec) 510 (mV/dec)
DG4 Tsi=50nm Tox,top=20nm Tox, bottom=50nm
470 (mV/dec) 1400 (mV/dec) 470 (mV/dec)
Table 4-1 The NTrap extracted from the SS and effective trap states concentration.
Table 4-2 The comparison of the trap states density ratio extracted from SS and Figs.
4-12 and 4-13
VITA
姓名:陳 玲
性別:女
生日:1983/09/13
籍貫:澳門
電子郵件:[email protected]
求學歷程:國立交通大學 電子研究所 2006/09~2008/06 國立交通大學 材料科學與工程學系 2002/09~2006/09
論文題目:
複晶矽雙閘極薄膜電晶體特性及電性擾動分析
A Study of Characteristics and Variability of Double-Gated Poly-Si Thin-Film Transistors