(b)
Fig.5-4 Interface trap densities for (a) 500OC (b) 400OC annealed devices
-2 -1 0 1 2
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.3
0.4 0.5 0.6 0.7 0.8 0.9 1.0
1kHz 10kHz 100kHz 1MHz Capacitance
(
uF/cm2)
Gate voltage (V)
(c)
Fig. 5-7 C-V curves of Pr6O11 (10nm)/In0.53Ga0.47As devices (a) PDA at 450OC. (b) PDA at 500OC (c) PDA at 550 OC. The hysteresis of 1MHz curves of two samples are shown in the inset figure.
Fig. 5-8 TEM image of 550OC annealed Pr6O11/In0.53Ga0.47As device
(a)
(b)
Fig. 5-9 (a) C-V curve, (b) TEM image and EDX analysis of CeO2(9nm)/In0.7Ga0.3As InP device.
Fig. 5-10 TEM image and EDX analysis of CeO2(8nm)/Pr6O11(4nm)/InAs device
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Fig. 5-11 Comparison of C-V characteristic between (a) one-step annealing process (only Pr6O11 was annealed at 500OC), and (b) two-step annealing process (Pr6O11 was first annealed at 500OC, second step annealing was performed at 400OCafter CeO2 deposition) for CeO2 (8nm)/Pr6O11 (4nm)/InAs devices
(a)
(b)
Fig. 5-12 TEM images of (a) one-step annealed and (b) two-step annealed CeO2 (8nm)/Pr6O11
(4nm)/InAs devices.
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Fig. 5-13 C-V curves of CeO2(6nm)/Pr6O11(4nm)/InAs devices of different annealing temperatures. (a) Pr6O11 was first annealed at 500OC, followed by 400OC annealing after CeO2 deposition. (b) Pr6O11 was first annealed at 550OC, followed by 400OC annealing after CeO2 deposition.
(a)
(b)
Fig. 5-14 TEM images of CeO2(6nm)/Pr6O11(4nm)/InAs devices first step annealed at (a) 500OC (b) 550OC. And both annealed at 400OC after 6nm CeO2 deposition. The Pr6O11 beneath the CeO2
transform from amorphous type to poly-crystalline as the annealing temperature increase
Table 5‐1 Extracted equivalent oxide thickness (EOT) from 10kHz curve of CeO2/Pr6O11/InAs devices
@10kHZ Two‐step annealed
One‐step annealed
Samples* A B C D
EOT(nm) 3.51 4.14 4.71 5.32
* A: CeO2 (6nm)/Pr6O11 (4nm)/InAs/In0.7Ga0.3As/In0.53Ga0.47As/InP (Pr6O11 first PDA at 550OC, CeO2 second PDA at 400OC) B: CeO2 (6nm)/Pr6O11 (4nm)/InAs/In0.7Ga0.3As/In0.53Ga0.47As/InP (Pr6O11 first PDA at 500OC, CeO2 second PDA at 400OC) C: CeO2 (8nm)/Pr6O11 (4nm)/InAs/In0.7Ga0.3As/In0.53Ga0.47As/InP (Pr6O11 first PDA at 500OC, CeO2 second PDA at 400OC) D: CeO2 (8nm)/Pr6O11 (4nm)/InAs/In0.7Ga0.3As/In0.53Ga0.47As/InP (Only Pr6O11 first PDA at 500OC)
Table 5‐2 Extracted equivalent oxide thickness (EOT) from 10kHz curve of HfO2
(9nm)/InAs devices
@10kHz PDA at 400OC PDA at 500OC
EOT(nm) 3.49 3.85
Chapter 6 Conclusion
The HfO2, Pr6O11 and CeO2/Pr6O11 were deposited on n-InxGa1-xAs for MOS capacitors studies. HfO2/In0.53Ga0.47As MOS capacitors showed good scalability with minimum EOT of 2.9nm for 6nm HfO2 device. The inversion behavior of the devices was also studied. The high frequency inversion behavior was more pronounced for device with high indium concentration, possibly due to the smaller band gap of InAs because it has higher intrinsic carrier concentration and shorter carrier life time, which resulted in short minority carrier response time which makes the carriers follow the small signal and form inversion layer. The PDA temperature for HfO2/InAs devices was also characterized. 400OC annealed device showed larger frequency dispersion than 500OC annealed device, which was possibly due to the high interface trap density.
Pr6O11 was used to replace HfO2 to increase the capacitance of the MOS capacitor, the capacitance was increased owing to the high dielectric constant, but the inversion behavior was not apparent due to high interface trap pinning of the Fermi level. High temperature annealing may unpin the Fermi level and form inversion layer, but it also resulted in deep-depletion phenomenon. The deep-depletion phenomenon could be due to more oxide charges were induced during annealing process, which can be examined from the hysteresis performance. Also the poly-crystalline structure provided the current leakage paths. To balance the charge lost due to inversion, depletion region will further expand exceeding its thermal equilibrium width, resulted in deep- depletion phenomenon.
The CeO2/Pr6O11 gate stack was also applied on InAs. Two step annealing process
was performed to increase the accumulation capacitance. The increase was due to the oxide thickness decrease during second step annealing process after CeO2 deposition.
The thickness of the gate stack was also characterized, CeO2(6nm)/Pr6O11 gate stack exhibited larger leakage current than 8nm CeO2 due to the decrease of physical thickness. Device annealed at 550OC showed more severe current leakage than device annealed 500OC, which was due to the poly-crystallized gate oxide.
As compared to HfO2 gated device, the CeO2/Pr6O11 gate stack structure didn’t show the high-k characteristics, which may due to the rough surface and poly-crystallized structure provided the current leakage path which caused the device unable to store charge sufficiently. But since both CeO2 and Pr6O11 have relatively high dielectric constant, especially for single crystal CeO2 with dielectric constant of 52, the CeO2/Pr6O11 gate stack would be the potential high-k stack candidate. As for HfO2
gated devices, due to its good scalability and thermal stability, and the well pronounced inversion behavior observed in high indium concentration InxGa1-xAs, the HfO2/InxGa1-xAs would be the most potential MOS devices in future CMOS industry.
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