In LTPS TFTs process, it bases on excimer laser crystallized poly-Si which contributes to random orientation of poly-Si grains, grain size variation, and incomplete termination of grain boundaries. These characteristics usually accompany a random device-to-device threshold voltage variation on panels which result in serious impacts on the accuracy of analog circuits [23], [24].
The threshold voltage variation impacts have been investigated in many aspects.
In [23], this paper investigates the threshold voltage variation effect on output buffer.
Without accurate threshold voltage, the common-mode of output voltage may change in a large-scale and further impact the operation of following stage.
Besides, [24] shows the impact of threshold voltage variation on gate-bias. If the threshold voltage may vary, the generated current will be different between TFTs even if the gate-bias is the same. Therefore, a threshold voltage compensation skill is needed to avoid these serious impacts on analog circuit.
3.2.2 Design of On-Panel Readout Circuit and Simulated Results
To compensate the impact of threshold voltage variation, a new readout circuit of capacitive sensor suitable for LTPS process has been proposed. The block diagram of the new proposed readout circuit is shown in Fig. 3.2 which consists of a transconductance amplifier, current integrator and a 4-bit ADC [26].
In the first stage, the input voltage is transformed into the current Iint which equals to VFin×Gm by the transconductance amplifier (Gm amplifier). Secondly, the
current Iint is converted into voltage Vo by charging the current integrator. The Vo can be expressed as:
Vo=
∫
K∗I dtint , (3.2)where K is a constant.
Since Iint is a function dependent on VFin and Vo is proportional to the integration of current Iint, from the equation above, the input signal will be amplified as time goes by. In addition, with 4-bit ADC, the proposed circuit can judge the different VFin caused by different touch position.
Figure 3.2 Block diagram of the new proposed capacitive touch panel readout circuit with 4-bit ADC.
~ 27 ~
Figure 3.3 Schematic of proposed readout circuit with threshold voltage compensation and its timing chart.
Fig. 3.3 shows the new proposed capacitive touch panel readout circuit with its timing chart. The circuit consists of five pTFT devices, one nTFT device and a loading capacitance Cout. M1~M5 are switches and M6 is in the charge of transconducting voltage into current as a Gm amplifier. The timing chart consists of three periods: (1) compensation period, (2) reset period, and (3) amplification period.
In the compensation period, M2, M3, M5, and M6 are switched on. The node Va is charged by the supply voltage VDDA until M6 is in cut-off region. The voltage difference between the source and gate of M6 equals to the threshold voltage of M6 (Vth6). In the meanwhile, the node Vc is set to the supply voltage VDDA. The voltage difference between node Va and Vc is stored on capacitor C1. In the reset period, M2 and M5 are switched off as well as M1 is switched on. Therefore, the
output voltage Vo is discharged to ground by M1 and the node Va maintains the same voltage (VDDA-|Vth6|). During the amplification period, the node Fin is connected to node Vc, dropping a voltage (∆V) which equals to the voltage difference between VDDA and VFin. Because of the charge conservation at the node Va, the voltage of node Va also drops ∆V and becomes equal to (VFin-|Vth6|). In addition, node Va should be discharged to ground in every cycle to guarantee that VDD-|Vth6| can be stored at the node Va successfully. If node Va is initially larger than VDDA-|Vth6|, the compensation operation doesn’t work because M6 turns off. The basic current formula of TFT device can be expressed as following equation:
( )
2 current integrator, the impact of threshold voltage variation on the output voltage Vo can be reduced as shown in Fig. 3.4. Because the range of threshold voltage variation cannot be provided by the foundry, the ±50% threshold voltage variation is applied according to [27], [28] in Fig. 3.4. The output voltages Vo for proposed circuit with~ 29 ~
threshold voltage compensation are almost the same. Compared to the readout circuit without threshold voltage compensation, the current Iint variation in amplification period can be reduced from 3120% to 29.3%. In additional to the threshold voltage variation, ±50% mobility variation is also simulated in the proposed circuit in Fig. 3.5.
The output voltages Vo of proposed circuit with mobility variation shows larger variation compared with that in Fig. 3.4 and the current Iint variation in amplification period can reduced from 3550% to 33%.
(a)
(b)
Figure 3.4 Simulated results of the proposed readout circuit for capacitive sensor (a) without threshold voltage compensation and (b) with threshold voltage compensation under different threshold voltage.
~ 31 ~
(a)
(b)
Figure 3.5 Simulated results of the proposed readout circuit for capacitive sensor with threshold voltage and mobility (µ0) variation (a) without threshold voltage compensation, and (b) with threshold voltage compensation.
3.2.3 Switch Design
In the proposed circuit, many switches are used to control the circuit operation.
The detail design is considered in this subchapter. Charge injection and clock feedthrough effects are discussed.
Charge Injection [31]
The conduction of MOS is based on the existence of a channel. When the gate of MOS is biased at an appropriate voltage, for NMOS, many electrons (or holes for PMOS) are attracted to the oxide-silicon surface and the channel is formed to conduct the current from the source to drain. The effect of charge injection is shown in Fig. 3.6.
Assuming Vin≈Vout, the total charge Qch in the inversion layer can be expressed as:
(
DD in th)
ch ox
Q =WLC V −V −V , (3.5)
where W represents the width of MOS devise, L denotes the effective channel length, Cox is the gate oxide capacitance per unit area, and VDD is the voltage level when clock is ‘1’. When the MOS switch is turned off, half of the charge will inject to both the source and drain terminal contribute to an error voltage equals:
( )
where the CH represents the output capacitance.
However, in real circuit, this charge which injects to the source and drain terminal is not exact half of the channel charge. It depends on the impedance of both sides. If the impedance of one side is approximately infinite, total channel charge will
~ 33 ~
flow to the other side.
Figure 3.6 Charge injection effect when a switch turns off.
Clock Feedthrough [31]
In additional to the error caused from charge injection, the MOS switch couples the gate clock through the gate-drain and gate-source overlap capacitance and further contribute to an another type error term. As shown in Fig. 3.7, this error can be
where Cov is the overlap capacitance per unit length.
This kind of error can be viewed as a constant offset if Cov is constant. Because it is independent of input level, post-calibration can be applied to cancel this offset perfectly. Besides, clock feedthrough is a trade-off between speed and precision. The response time of touch panel is in millisecond order which is a slow process. Hence, the clock feedthrough effect is not obvious in circuit of touch panel.
Figure 3.7 Clock feedthrough effect when a switch turns off.
Based on the formula mentioned above, both errors are proportional to the length and width of MOS switch. Therefore, in the proposed circuit, the switch is designed with the minimum width 3µm and minimum length 3µm. Although the smaller size of MOS devices will result in slower operation speed for circuit, the demand for touch panel response time is between tens Hz which is not a quite high value.
~ 35 ~
Figure 3.8 Circuit configuration of A/D converter.
Fig. 3.8 shows the configuration of ADC suitable for LTPS technology [29], [30].
Again, the switch capacitor technique is applied to cancel the influence of threshold voltage variation of TFT device. All switches are controlled by the clock signals CLK5 or CLK6. The circuit operation has two steps, (1) storing the logic threshold voltage Vth,log on capacitor and (2) compensating Vth,log and comparing Vo with the reference voltage. At first, CLK6 is set to high and the difference between logic threshold voltage Vth,log of inverter and Vref is stored on the capacitor C2. In the comparison period, CLK6 is switched to low and CLK5 is set to high. Due to charge conservation, the input voltage of inverter becomes (Vo+Vth,log-Vref). Two inverter stages as buffer are added to guarantee full-swing of the output voltage.
Furthermore, this circuit also has immunity from threshold voltage variation since the Vth,log is cancelled by storing itself on C2. Four-bit resolution is achieved by using four same ADC structure with different reference voltages Vref1~Vref4 as shown in Fig. 3.9. Fig. 3.10 shows the simulated result of the proposed circuit under the non-touch event with the digital output code of ‘1111’. Fig. 3.11 shows the
simulated results of the proposed readout circuit under different Ct. The digital code of ADC presents ‘1110,’ ‘1100,’ ‘1000,’ and ‘0000’ under Ct = 1pF, 2pF, 3pF, and
>3pF, respectively. Depending on the digital bits of Vout, different touch position between two sensor lines can be judged by interpolation method and the overall resolution for touch panel can be enhanced.
Figure 3.9 The 4 bits on-panel readout circuit of capacitive sensor suitable for LTPS process.
~ 37 ~
Figure 3.10 The simulated result of the proposed circuit under the non-touch event with the digital output code of ‘1111’.
The number of sensor lines on panel is limited. If the readout circuit can only distinguish whether the panel is touched or not, when the area between two sensors lines is touched, this kind of circuit cannot judge the correct position but choose one sensor line as the touched side. If the readout circuit can distinguish the different capacitance value due to different touch area, the interpolation method can be utilized to identify the more accurate position without more sensor lines and further to enhance the resolution for touch panel applications. The method for extracting touch position has been shown in Fig. 3.12. As shown in Fig. 3.12, when the touch position is between two sensor lines, the approximate touch position can be calculated by the equation:
the induced capacitance between touch object and sensor line, and WY is the distance between two sensor lines. Since Ca and Cb can be judged by digital codes, more output bits from ADC can gain the higher resolution for touch panel applications.
(a) (b)
(c) (d)
Figure 3.11 The simulated results of the proposed readout circuit with (a) Ct = 1pF (digital output code: ‘1110’), (b) Ct = 2pF (digital output code: ‘1100’), (c) Ct = 3pF (digital output code: ‘1000’), and (d) Ct > 3pF (digital output code: ‘0000’).
~ 39 ~
Figure 3.12 The diagram of panel touched by finger.
3.3 Summary
An on-panel readout circuit for capacitive sensor has been designed and simulated. Using the proposed threshold voltage compensation technique, the output current can be reduced from 3120% to 29.3%. With 4 bits ADC, 4 different capacitances can be sensed. The interpolation method can be utilized to enhance the resolution for touch panel applications.
Chapter 4
Measured Results of On-Panel Readout Circuit for Capacitive Touch Panel
4.1 Measurement Setup
The new proposed circuits have been designed and fabricated in a 3-µm LTPS technology. The layout view of proposed circuit has been shown in Fig 4.1. Fig. 4.2 shows the die photo of the fabricated readout circuit with Indium Tin Oxide (ITO) on glass substrate, where the ITO is utilized to verified the sensor line. When the finger touches the ITO, the touched area between ITO and finger results in capacitance change on the sensor line. The larger area is touched the larger capacitance change on the sensor line. The ITO is drawn with the equivalent resistance of 150 kΩ in the square form instead of a line in Fig. 4.2 due to the limitation of layout area in the experimental chip. The area of ITO is 1020 µm x 2770 µm and the area of on-panel readout circuit with threshold voltage compensation is 515 µm x 930 µm. Fig. 4.3 shows the fabricated circuit on glass substrate to verify the readout function of the proposed circuit, when the ITO on the glass substrate is touched by a finger. The 4-bit digital output code is utilized to identify the different touch area and to enhance the resolution of the touch panel. The measurement setup is shown in Fig. 4.4, where the touch capacitance Ct is measured by precision LCR meter of Agilent 4284A, CLK1 to CLK6 are given by Keithley 4200 dual pulse generator, power supply is GPS 4303 DC power supply and the output waveforms are observed by SDO603A oscilloscope.
The touch capacitance (Ct) is measured by Agilent 4284A. Through connecting the two ports of one stand-alone ITO, which is especially designed to be touched for capacitance measurement with this instrument, the change of capacitance of ITO can
~ 41 ~
be detected. Therefore, the touch capacitance value with different touch area can be also detected.
Figure 4.1 The layout view of proposed circuit.
Figure 4.2 The die photo of the fabricated readout circuit with Indium Tin Oxide (ITO) on glass substrate.
Figure 4.3 The fabricated circuit on glass substrate to verify the readout function of the proposed circuit.
~ 43 ~
Figure 4.4 The fabricated circuits on glass substrate to verify the readout function of the proposed circuit and its corresponding measurement setup.
4.2 Measured Results
The fabricated readout circuit is first verified with the externally applied input signals (VFin). Fig. 4.5 shows the measured result of the fabricated circuit under non-touch event (Ct = 0pF), where the digital output code is ‘1111.’ Fig. 4.6 shows the measured results of the fabricated circuit under different Ct. The digital output code shows ‘1110,’ ‘1100,’ ‘1000,’ and ‘0000’ under Ct = 1pF, 2pF, 3pF, and >3pF, respectively.
Figure 4.5 The measured result of the fabricated circuit under non-touch event (Ct = 0pF) with the output code of ‘1111’.
(a)
~ 45 ~
(b)
(c)
(d)
Figure 4.6 The measured results of the fabricated readout circuit verified with the Ct of (a) 1pF (digital output code: ‘1110’), (b) 2pF (digital output code: ‘1100’), (c) 3pF (digital output code: ‘1000’), and (d) >3pF (digital output code: ‘0000’). The corresponding digital codes can be successfully generated at the output Vout1, Vout2, Vout3, and Vout4.
After the successful verification of readout function, the fabricated chip is measured by the different touch area of the finger with a 100-pF capacitor connected to the VFin node, which is used to simulate the touching event modeled in Fig. 3.1.
The different digital output codes are confirmed according to the different touch area of ITO. Fig. 4.7 shows the measured result of the fabricated circuit under non-touch event, where the digital output code is ‘1111.’ Fig. 4.8 shows the measured results of the fabricated circuit under different touch area. The digital output code shows ‘1110,’
‘1100,’ ‘1000,’ and ‘0000’ when the touched area by finger is covered with less than
~ 47 ~
1/4, 1/2, 3/4, and full of the ITO area, respectively. By further analyzing the 4-bit digital codes, the corresponding functions, such as zoom in, zoom out, move, and so on, can be performed on the touch panel by the appropriate algorithm of software in the system.
Figure 4.7 The measured result of the fabricated circuit under non-touch event.
(a)
(b)
~ 49 ~
(c)
(d)
Figure 4.8 The measured results of the fabricated readout circuit under the touched area by finger covered with (a) less than 1/4, (b) 1/2, (c) 3/4, and (d) full of the ITO area.
Chapter 5
Conclusions and Future Works
5.1 Conclusions
A readout circuit for capacitive sensor on glass substrate for panel application has been successfully designed and fabricated in a 3-µm LTPS technology. The switch capacitor technique is applied to enlarge the input signal and eliminates the influence of threshold voltage variation successfully. This new proposed circuit architecture can not only distinguish the panel is touched or not, but also distinguish different value of touch capacitance and further know the touch position between sensor lines by utilizing interpolation method. In additional to threshold voltage variation, mobility variation has been successfully verified. The current difference is controlled in a workable region.
5.2 Future Works
Although the proposed circuit has achieved the basic threshold voltage compensation function successfully, the clock number should be further reduced to lessen the circuit design complexity. Besides, this ADC configuration costs much power because when the ADC is in the compensation period, a static current flows through power supply to ground. Although this ADC structure has immunity from threshold voltage variation, when the switch is in transient state, the noise from charge injection or clock feedthrough could trigger the inverter and contributes to malfunction. Therefore, based on these two reasons, another ADC with immunity from threshold voltage variation should be chosen.
~ 51 ~
Furthermore, the noise (like thermal KT/C, and so on) and power domain will contribute to second order effect on the Gm amplifier. It should be further analyzed.
APPENDIX
In the fabricated circuit, the clock generator is not included but external clock is applied. However, for real products, the clock cannot be applied externally but use clock generator to generate all clocks required. Therefore, in the appendix, the clock generator circuit is shown in Fig. A.1. Only one input CLK4 is required to generate remaining clocks. Fig. A.2 shows the simulated results of clock generator.
CLK1~CLK6 is generated by this circuit successfully.
Figure A.1 The schematic of clock generator with one input CLK4.
~ 53 ~
Figure A.2 The clocks CLK1~CLK6 generated by clock generator.
CLK3 CLK1
CLK2
CLK4
CLK5
CLK6
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