Chapter 2 Principle and Design
2.3 Device design
2.3.6 Mechanical switch control analysis
The mechanical switches SW1 and SW2 are shown in Fig. 2.3 and Fig.2.4.
Traditionally, the switches utilize diodes or clocked active switches [35, 36]. But charge leakage and reverse current issues exists in this circuit. A reverse current should be lower than a few nA in order to prevent charge leakage. However, this is not
(a)
(b)
common in commercially available diodes and other switching circuitry. Mechanical switches are utilized due to the barely zero charge leakage and lower power consumption. Other advantages are the synchronous operation to the variable capacitor and the monolithic integration with the device structure.
The detail of mechanical switch design was already presented in [27]. This section will discuss the power loss issue during the mechanical switches control process. SW1 is a contact mechanism switch. The variable capacitor charging is realized by SW1 turning on when the comb fingers of the variable capacitor touch.
Mechanical switch SW2 is controlled by the pull-in voltage. When the voltage on the capacitor reaches the pull-in voltage, the node B will move to touch node C by electrostatic force, as shown in Fig. 2.5. The pull-in voltage can be determined by the following equation (Fig.2.5), and L is the total overlap length of nodes B and C. The thickness h is the same as the variable capacitor. A number of parameters influence the pull-in voltage.
Shown in Fig. 2.18 (a) is the time response of voltage on the variable capacitor and movable fingers displacement. The figure shows the SW2 turn on precisely when the fingers move to the middle position. The output power will fit in with the theoretical value as mentioned above if the device has no leakage current issue. The maximum voltage Vmax on the variable capacitor is 14 V, which is related to the ratio of maximum and minimum capacitance,
max
max in
min
V C V .
= C (2.27) The pull-in effect occurs at one-third of initial gap between the node B and C. Fig.
2.18 (b) has the low pull-in voltage. It shows that the SW2 closes before the fingers moving to the middle position, which is caused by the soften spring constant of SW2.
The voltage on the variable capacitor was lower extremely than Vmax when SW2 closes. It indicates the incomplete energy conversion and means the output power loss.
Shown in Fig. 2.18 (c), the voltage on the variable capacitor reaches Vmax but the SW2 turn on lately. It indicates that the fingers are pulled by a larger restoring force of hard spring. From the simulation result, we can find the relationship between the timing error and power loss, as shown in Fig. 2.19.
Fig. 2.18 SW2 closes (a) on time (b) early (c) late (a)
0.98 0.982 0.984 0.986 0.988 0.99 0.992 0.994 0.996 0.998 1 -5
0 5x 10-5
time(s)
finger displacement(um)
0.98 0.982 0.984 0.986 0.988 0.99 0.992 0.994 0.996 0.998 10 5
0.98 0.982 0.984 0.986 0.988 0.99 0.992 0.994 0.996 0.998 1 -4
0 4x 10-5
fingers displacement(um)
0.98 0.982 0.984 0.986 0.988 0.99 0.992 0.994 0.996 0.998 10 5
Finger displacement (μm) Voltage on variable capacitor (V)
40
Time(s)
Fig. 2.18 SW2 close (a) on time (b) early (c) late (continued)
Fig. 2.19 Output power loss versus timing error
2.4 Layout design
The layout of the movable plate was discussed in the last section. This whole schematic was designed with a symmetric configuration to maintain the mass balance and ensure the stable movement in the x-direction during vibration. The minimum center width of movable plate should be larger than 1000 μm to maintain a high rigidness. With the external mass removed, more space in the center was to design the
-2.50 -2 -1.5 -1 -0.5 0 0.5 1
timing offset on SW2 turn on
power loss(%)
Timing offset on SW2 turn on (ms)
Power loss (%)
(c)
0.98 0.982 0.984 0.986 0.988 0.99 0.992 0.994 0.996 0.998 1 -4
0 4x 10-5
Time(s)
Finger displacement(um)
0.98 0.982 0.984 0.986 0.988 0.99 0.992 0.994 0.996 0.998 10 4
Voltage on variable capacitor (V)
Finger displacement (μm)
Time(s) 40
-40
finger cells to achieve the maximum output power. 8 mechanical springs are connected to the movable plate. The anchored areas of springs are minimized in order to reduce parasitic capacitance. The whole layout is shown in Fig. 2.20. The contact pads will be wire bonded to a printed circuit board for measurement.
Fig. 2.20 Layout view of the variable capacitor and switches
Fingers SW1
SW2
Spring
Movable plate Anchored area
2.5 Previous design and improvement
The layout of the previous design was shown in Fig. 2.21. The mechanical structure was designed to generate the output power of 31 μW. An external mass of 4 grams was put on the central hole in order to adjust the device resonance to match the input vibration. Two integrated mechanical switches, SW1 and SW2, were used to provide accurate charge-discharge energy conversion timing. Detailed parameter was listed in Table 2.3
Fig. 2.21 Layout view of the previous device
Lf
d Central hole
SW2
SW1 Spring
Fingers
Table 2.3 Design parameter for previous device
Variable Description of variables Designed value
h Device thickness 200 μm
Wf Finger width 10 μm
Lf Finger overlap length 400 μm
d Finger initial gap 26 μm
t Silicon nitride sidewall thickness 500 Å Cmax Maximum value of capacitance 1570 pF Cmin Minimum value of capacitance 62 pF
k Mechanical spring const. 2425 μN/μm
m Mass of movable plate 4 g
RL Driven load resistance 50 MΩ
Cstor Output temporary storage capacitor 5 nF Vout Output voltage (steady state) 40 V Pout Output power (steady state) 31 μW
However, the leakage issue was existed in the previous device. The front side of our previous SW1 layout is shown in Fig. 2.22 (a). Guarding walls was used to maintain the same trench width during the ICP etching process. They are removed after releasing process. But the guarding walls may stick on the anchor sidewall during the releasing and then cause leakage issues. Therefore, the guarding walls are replaced, as shown in Fig. 2.22(b). Furthermore, the width of gap was identical to maintain the same etch rate during deep reactive ion etching.
Fig. 2.22 (a) Front side SW1 layout view in our previous design (b) modified design
Second, the overlap region between the movable plate and substrate was considered, as shown in Fig. 2.23. The device was fabricated in SOI wafers with an insulation layer thickness of 2 μm. But parasitic capacitance and leakage resistance are produced during the spring movement in the overlap region. In order to avoid this issue, the substrate area under the movable plate, especially in the spring and switch regions should be reduced. The advantage of the method is to reduce the parasitic capacitance and alleviate the leakage resistance problem. Subsequently the modified device was fabricated in SOI wafer and was discussed in Chapter 3.
Fig. 2.23 (a) Overlap region between fingers and substrate (b) overlap region removal
(a) (b)
2.6 Summary
The design and analysis of a vibration-to-electric energy converter with no external mass attached on the device is presented in this chapter. For the 0.3 V supply voltage and 1cm2 chip area constraints, this device can be designed to generate 0.51 μW for the input vibration with frequency of 120 Hz. Compared our previous design with metal ball attachment, the device has the better output power density and alleviate the structure damage caused by the ball during the vibration. Our previous design was modified to avoid the leakage resistance between the device layer and the substrate. Fabrication and measurement results will be discussed in the following chapters
Chapter 3 Fabrication Process
The detail of fabrication process flow and encountered process issues in the SOI (Silicon on Insulator) based device will be presented in this chapter. The first part of this chapter shows the process based on the SOI wafer. The process includes the steps such as wafer cleaning, photolithography, deep reactive ion etching, structure releasing, and metal deposition. The second part will discuss the process issues which were encountered in the experiment. The problems were solved and devices were successfully fabricated.
3.1 Fabrication process flow
As mentioned above, the high aspect ratio MEMS structures for the comb fingers are used as the variable capacitor to convert energy. The structure is fabricated by the deep reactive ion etching technology such as the Inductively Couple Plasma (ICP) etching. The comb fingers are the moving electrodes of the variable capacitor. The outer frame serves as the electrodes of the fixed fingers.
In order to acquire the best output power, the device thickness should be as large as possible. It is limited by the ICP fabrication capability to define the finger structure.
The resistive loss was reduced by using a highly conductive device layer with the resistivity less than 0.02 Ω-cm. The buried oxide layer is 2 μm. The handle layer is 400 μm for a firm structural support.
Most of the fabrication was conducted in the Nano Facility Center at National Chiao Tung University. The fabrication process is illustrated in Fig. 3.3 and the detail of the parameters in every process step is presented in the following.
Step 1: Wafer cleaning
The RCA clean is the industry standard for removing contaminants from wafers.
It should be performed before high temperature processing steps. The procedure has three major steps in sequence:
A. Organic Clean: Removal of insoluble organic contaminants B. Oxide Strip: Removal of the thin silicon dioxide layer.
C. Ionic Clean: Removal of ionic and heavy metal atomic contaminants.
The SOI wafer is used in this experiment, as shown in Fig. 3.1(a). Detailed parameters and steps are given as below. Every step begins and ends with 5 minute de-ionized water (DI water) rinse.
Step Process parameters Function
1 H2SO4 : H2O2 = 3 : 1 (10 min 85 °C) Organic removal 2 HF : H2O = 1 :100 (room temperature 30 seconds) Chemical oxide removal 3 NH4OH : H2O2 : H2O = 1 : 4 : 20 (10 min 85 °C) Particle removal 4 HCl : H2O2 : H2O = 1 : 1 : 6 (10 min 85 °C) Ion removal 5 HF : H2O = 1 :100 (room temperature 30 seconds) Chemical oxide removal
Step 2: Silicon oxide deposition on the backside
Silicon oxide was deposited by a BR-2000LL plasma enhanced chemical vapor deposition (PECVD) system on the back of the handle layer of the SOI wafer, as shown in Fig. 3.1(b). The silicon oxide is used as the hard mask for the back side ICP etching process due to the superior heat dissipation in ICP etching and convenience on the double side photolithography. The 4.5μm silicon oxide was needed according to the selectivity of 100:1 between silicon and silicon oxide in the ICP process.
Deposition was divided into several 2.2 μm steps to prevent cracking of oxide layer due to residual stress. Detailed parameters are given as below.
Description Process parameters
SiH4 flow rate 5 sccm
N2O flow rate 90 sccm
Process pressure 400 mTorr
Process temperature 350 °C
RF power 11 W
Deposition rate 35 minutes resulting in 2.2 μm (repeat 2 times)
Step 3: Back side photolithography on silicon oxide
The back side photolithography was performed by EV620 aligner on the silicon oxide deposited in the last step, as shown in Fig. 3.1 (c). The photoresist was AZ4620 due to its available thickness in the spin coater. The thickness of AZ4620 was 7 μm according to the selectivity between AZ4620 and oxide in the buried oxide etchant (BOE). Detail parameters are given as below.
Step Description Process parameters
1 HMDS coating 150 °C 30 minutes
7 Development 80 seconds
8 DI water Rinsing 90 seconds
9 Hard bake 120 °C at least 1 hour
Step 4: Wet etching on the back side
This step is shown in Fig. 3.1(d). The silicon oxide below the photoresist was etched by a buffered oxide etchant (NH4F: HF=6:1) with an etch rate of 1 μm per minute roughly. BOE solution is used due to the relatively low selectivity between
silicon oxide and photoresist in the RIE process. The undercutting effect of wet etching is irrelevant to cause the back side pattern for partial substrate removal. The samples can be immersed into DI water to dilute BOE solvent, which can protect the photoresist mask to avoid the BOE attack and alleviate the peeling off of the photoresist mask problem. Moreover, the photoresist mask also can be hard baked for at least 1 hour before the wet etching.
Step 5: Front side photolithography
The front side photolithography was performed by an EV620 double side aligner to define the photoresist mask, as shown in Fig. 3.1(e). The subsequent ICP etching is the primary process to define the device structure. In order to protect the structure in the device layer, the front side photolithography is performed after the back side process. The photoresist thickness is 5 μm because the minimum selectivity of ICP etching between silicon and AZ4620 photoresist is 40:1. Hard bake should be as long as possible to withstand the ICP etching. Detailed parameters are given as below.
Step Description Process parameters
1 HMDS coating 150 °C 30 minutes
2 1st spin (spread cycle) 500 rpm 10 seconds 3 2nd spin (spin cycle) 4000 rpm 40 seconds
4 Static settlement 10 minutes
5 Soft bake 90 °C 7 minutes
6 Exposure 11 seconds
7 Development 60 seconds
8 DI water Rinsing 90 seconds
9 Hard bake 120 °C at least 1 hour
Step 6: Deep reactive ion etching of the front side
The silicon structure in the device layer is defined by ICP etching which is performed by using a STS MESC multiplex ICP reactor with standard Bosch process, as shown in Fig. 3.1(f). By applying the etching and passivation parameters, it can provide a better etching profile. The detail was discussed later. In order to maintain the uniform etch rate and acquire the better heat dissipation, maximum helium leak rate should be limited. The averaged etch rate is roughly 2 μm per minute. Detailed parameters are given as below.
Description Etch phase parameters Passivation phase parameters
Time per cycle 11.5 seconds 7.0 seconds
SF6 flow rate 130 sccm 0 sccm
Helium back side pressure = 10 Torr Maximum helium leak up rate = 20 mTorr/min Etch rate 0.6-0.7 μm per cycle depending on pattern
Step 7: Wafer dicing
Wafer dicing must be performed before the back side deep silicon etching. The reason is that the entire wafer becomes very fragile and may disintegrate in the reactor chamber when a large area of the back side silicon is removed. The other problem is that the residual stress in the buried oxide can damage the structures in the front side layer. Therefore, the wafer is diced first by a Disco 2H/6T system. The device layer structures are protected during the dicing process by AZ4620 photoresist. The detailed
parameters of the protection photoresist coating are given as below. The subsequent back side etching will be conducted with the individual chips bonded to a carrier wafer by heat dissipation paste.
Step Description Process parameters
1 Removed the photoresist mask A.C.E or H2SO4 to remove 2 1st spin (spread cycle) 500 rpm 10 seconds 3 2nd spin (spin cycle) 1800 rpm 40 seconds
4 Soft bake 20 minutes
Step 8: Back side deep reactive ion etching
The wafer was diced as shown in the previous step. Diced chips were bonded on a handle wafer. In order to prevent the rupture of the handle wafer, silicon oxide or AZ4620 should be deposited on the handle wafer to avoid the plasma attacking during the ICP process before the chip bonding. The process of the back side ICP etching was shown in Fig. 3.1 (g). Heat dissipation issue was encountered due to poor helium cooling capability on the bonded chip. Moreover, the bonded chips in ICP etching process will spoil the selectivity and vertical profiles due to the helium capability degrade. Fortunately, the back side structure is rather insensitive to or even benefiting from non vertical etching profiles. Detail process parameters are identical to the front side ICP process.
Step 9: HF Releasing
The device chip is released by 49 % HF to remove the unwanted buried oxide and the blocking structure on the handle layer. The process is shown in Fig. 3.1 (h).
HF vapor also can release the device but has poor selectivity than solution. The release time is about 20 min and the oxide layer is over etched in order to prevent
leakage during metal deposition. Finally, the device is cleaned by rinsing in isopropanol (IPA) and then hot baked after the release is finished. DI water cannot be used to clean to avoid the stiction between the comb fingers in the release process.
Step 10: Silicon nitride deposition
As shown in Fig. 3.1 (i), silicon nitride is treated as the dielectric layer which was deposited by plasma-enhanced chemical vapor deposition (PECVD). HF releasing process is prior to this step due to poor selectivity between the silicon nitride and HF solution. A 2500 Å thick silicon nitride thickness was deposited on the top and bottom sides of the release chip. The sidewall nitride was expected as 500 Å because of poor step coverage in the PECVD process. Detailed parameters are given as below.
Description Process parameters
SiH4 flow rate 20 sccm
NH3 flow rate 80 sccm
Process pressure 400 mTorr
Process temperature 350 °C
RF power 10 W
Deposition rate 15 minutes resulting in 2500 Å
Step 11: Silicon nitride removal in anchor area
After the silicon nitride was deposited, the top side silicon nitride layer on the anchor area should be removed by a SAMCO RIE-10N RIE in order to provide the electrical contact to the silicon device, as shown in Fig. 3.1 (j). To prevent the leakage between the fingers, the silicon nitride deposited on the top side of the comb finger cannot be removed. With the shadow mask A in Fig. 3.1 (j), the silicon nitride is protected in the RIE process. Detail parameters are given as below.
Description Process parameters
SF6 flow rate 30 sccm
CHF3 flow rate 10 sccm
Helium back side cooling 15 sccm
Process pressure 50 mTorr
RF power 100 W
Etch rate 1000 Å per minute
Step 12: Metal deposition
As shown in Fig. 3.1(k), aluminum is deposited on the contact pads and the lateral contacts in the mechanical switches. Sputtering is used due to the better step coverage on the switch contacts. With the shadow mask B in Fig. 3.1 (k), aluminum is only applied to the contact pad and switch gap areas to prevent the leakage.
Step 13: Wire bonding and external mass attachment
The last two steps are to wire bond the contact pads to a PCB and then attach the external tungsten ball to the center hole for further vibration test, as shown in Fig. 3.1 (l). The chip is attached on the PCB board with silver glue before wire bonding. The ball has a mass of 4 grams and attached by epoxy. The care must be taken in this step or the device may be destroyed.
(a) RCA cleaning (Step 1)
(b) PECVD silicon oxide deposition on the back side (Step 2)
(c) Silicon oxide patterning by photoresist (Step 3)
Photo resist Oxide
Silicon Nitride Aluminum
(d) Silicon oxide hard mask etching by BOE (Step 4)
Fig. 3.1 Fabrication process flow of the SOI device
(e) Front side photoresist patterned by double side photolithography (Step 5)
(f) ICP deep silicon etching on the front side (Step 6)
(g) Back side ICP deep silicon etching (Step 8)
Photo resist Oxide
Silicon Nitride Aluminum
Fig. 3.1 Fabrication process flow of the SOI device (continued) (h) Release in HF solution (Step 9)
(i) Silicon nitride deposited by PECVD (Step 10)
Shadow mask A
(j) Top side silicon nitride removal by RIE with shadow mask A (Step 11)
(k) Metal deposition by sputtering with shadow mask B (Step 12) Shadow mask B
Photo resist Oxide
Silicon Nitride Aluminum
Fig. 3.1 Fabrication process flow of the SOI device (continued)
Fig. 3.1 Fabrication process flow on the SOI device (continued)
3.2 Processing issues and solution
Several problems and issues were encountered in the fabrication process. Most of issues or problems are related to the ICP etching process. Other issues are leakage issues due to incomplete isolation layer deposition. Solutions are proposed and demonstrated in this section.
3.2.1 Non ideal effects of the ICP process
Non ideal effects exist in the ICP process due to experiment inaccuracy. The effects include notching, loading effect, and grass formation etc. The detail process will be shown in the following.
Notching effect
Deep reactive ion etching through the silicon device layer is an essential step in microstructure fabrication. However, plasma etching the silicon over an insulator layer has a silicon notching problem at the silicon/insulator interface. The
Tungsten ball Switch Fingers
(l) Wire bonding and tungsten ball attachment (Step 13)
phenomenon was shown in Fig. 3.2 [37]. The positive charge accumulation in the isolation layer causes further deflection of reactant ion and forwarding scattering. The poor profile caused by the notching may result in degraded performances. As this undercutting is aspect ratio dependent, the profiles and the characteristics of the final devices may further vary across the wafer, affecting the repeatability and reliability, especially for the thick device wafer.
Fig. 3.2 Notching effect [37]
The problem was encountered in our device structure, as shown in Fig. 3.3 (a).
The bottom of the comb finger was over etched due to the plasma bombarding on the interface between silicon and oxide layer. Therefore, the deep ion etching was divided into two steps to prevent the silicon over etching. First, the etch rate of the deep silicon etching should be controlled accurately. Thus, the comb fingers should be
The bottom of the comb finger was over etched due to the plasma bombarding on the interface between silicon and oxide layer. Therefore, the deep ion etching was divided into two steps to prevent the silicon over etching. First, the etch rate of the deep silicon etching should be controlled accurately. Thus, the comb fingers should be