Chapter 3 Behavioral Simulation of the Proposed CDR
3.4 Transceiver Simulation
Send
Fig. 3-21: Transceiver system
The goal of our design is to send 32-bit control signal from the transmitter through the power line of the automobile. Then, we despread the chips and send the data to the driver circuit. We know that the data length is 32-bit. So the transmission is burst-mode. Therefore every time a set of control data is sent, the CDR needs to resynchronize each time. Preamble is a sequence of known bits which are sent in each frame. It is used for synchronization. The length of the preamble should be long enough to let the CDR synchronize and recover the data properly. Consequently, at transmitter end, the preamble is sent before the control data and a counter is used for select the output of the MUX. At receiver end, a sequence detector is used to detect the pattern of preamble and control the serial-in parallel-out (SIPO) circuit. A timing control circuit between them is used to control the clock of the SIPO circuit, for it
sends out the control data correctly. Fig. 3-22 shows the transmitter end, and fig. 3-23 shows the receiver end.
Mode 1
Preamble
32-bit Control Data
Output of MUX
Clk
Fig. 3-22: Transmitter
Data from TX
Data from CDR
Clk
Get
Send
P0
P1
P2
P3
1 1 0 1
Fig. 3-23: Receiver
As shown in Fig. 3-22, when mode1 becomes high, the data will be serialed out. In Fig.
3-23, we can see that the CDR is in code acquisition at first. To recover the data, the preamble must be detected to set the Get and Send signals and trigger the deserializer. P0 to P3 are the first four data bits.
Chapter 4
Circuit Implementation of the Transceiver
4.1 Transmitter
4.1.1. Barker Code Generator
Barker
Fig. 4-1: Barker code
As Fig. 4-1 shows, the Barker code generator is a shift register which the output is connected to the input. The sequence of Barker code is {00011101101}, it is implemented by setting and resetting the DFF.
4.1.2. Serializer
Clk/32 will load 32-bit control data firstly and SEL will be high for a period of Clk and load the data to the input of DFFs. The DFFs serial out the data. The SEL signal is generated from the circuit shown in Fig. 4-3.÷32 DFF DFF
Fig. 4-3: Control signal for serializer
4.1.3. Preamble and Counter
The preamble sequence is {1010…….1011}. For the worst case, the synchronization for CDR needs to delay 11 chip times. It is equivalent to 33 times of phase shifting. We overdesign the sequence length to prevent any problem which may influence the synchronization. Therefore, the length is 42-bit. We use a 6-bit synchronous counter to generate the preamble and control the MUX and the serializer of the transmitter. We use the least significant bit (LSB) of the counter as the preamble sequence but the last two 11 pattern is different from the other. When the counter counts to 41, the NOR output will be high and
trigger the DFF to make the OR output high. So, the preamble will be high all the time. The control signals of the MUX and the serializer are produced in the same way. Both signals will be high when the counter counts to 43 and 40.
Fig. 4-4: Preamble and counter
4.2 Receiver
4.2.1. Accumulator
The accumulator consists of four half adders and a 4-bit DFFs. The input of accumulator is 1-bit and its output is 4-bit. The carry-out of the half adder connects to the input of the next half adder except the last one. The DFFs store the sums of the half adders for the next time, their output connect to the input of the half adder.
DFF
4.2.2. Absolute Value Circuit
According to the Fig. 3-2, we have already known the input and output of the absolute value circuit. It is a combinational circuit. The truth table is as follow:
1
Fig. 4-6: Absolute value circuit
4.2.3. Threshold Detector
The threshold detector is a 4-bit magnitude comparator. The output of the comparator will be high when the input is greater than the value we have set. The value is 3 for the code acquisition and code tracking loop and 6 for despread the data.
4.2.4. Confidence Counter
The confidence counter is encoded as an one-hot-state state machine. The input leadand lagsignals control the output of the MUX in order to shift 1 left or right. Fig. 4-7 shows the circuit of confidence counter.
Lead/Lag
Fig. 4-7: Confidence counter
4.2.5. Phase Control FSM
The circuit of the phase control FSM is similar to the confidence counter, we use the state assignment as its output.
LeadOV/LagOV
Fig. 4-8: Phase control FSM
4.2.6. Clock Generator
The chip rate is 11MHz and the data rate is 1MHz. We need to generate three phases of 11MHz. The clock generator is a Johnson counter, it uses 66MHz clock to generate 6 phases of 11MHz, and we only take 3 of them as the sampling clocks.
DFF
Fig. 4-9: Johnson counter
4.2.7. Delay Adjustment
As we have mentioned before, the phase rotation needs a proper delay to prevent the race
condition. So we design the following circuit to realize the delay signal.
Fig. 4-10: Delay circuit for Ph+ phase
DFF
Fig. 4-11: Delay circuit for Php phase
4.2.8. Sequence Detector
The sequence detector is used to detect the sync pattern {1011} in the preamble sequence.
Its state diagram is as follows. When it detects the pattern, it will send a Get signal to indicate that the following data are the control signals. The serializer will start to function.
S0: initial
Fig. 4-12: State diagram of sequence detector
Preamble from TX
Data from CDR
Clk
Get
Fig. 4-13: Simulation of the sequence detector
4.2.9. Timing Control
The timing control circuit is used to control the divider and the deserializer. At first, the sequence detector recognizes the preamble and sends the Get signal. Then, the timing control circuit receives the Get signal and enables the divider and the deserializer by the Send signal.
The divider divides the retime clock by 32 and generates Clk/32 used in the deserializer. The deserializer starts to receive the 32-bit control data and send to the backend driver circuit in parallel form. After sending out the 32-bit control data, the timing control circuit will disable the divider and deserializer. The deserializer stores the control data until the next new control data is sent.
DFF
Rst
DFF
Rst
DFF
Rst
DFF
Rst
DFF
Rst
DFF
Rst
Clk Rst 1
Get Send Clk/32
Fig. 4-14: Timing control circuit
4.2.10. Deserializer
The deserializer is a conventional one. The simplest structure is suitable enough for our application.
4.3 Circuit Simulation of the Transceiver
We use SPICE to perform the circuit simulation of the entire system. Firstly, the channel is assumed to be ideal. We build up the transmitter and the receiver. Then, we adjust the start time of the transmitter and let the transmitted chips have some delay with respect to the local Barker code at receiver end. We test whether the phase rotation scheme can recover the data correctly or not. As shown in Fig. 4-17, leadOV has been high for 14 clock period. It means
Fig. 4-16: Simulation of the transmitter
Data
Fig. 4-17: Simulation of the receiver
We can observe that the backend circuit can function well to output the data in parallel.
Next, we change the frequency of clock at the transmitter end to examine if the CDR can shift the phases to correct the frequency error or not.
Data
Fig. 4-18: Simulation of the frequency error
We let the clock of the transmitter faster than the clock of receiver. The total run length is
80 data bits. We set the frequency error to 3250ppm. It will underflow 1 chip about every 307.7chips. The total number is about 880 chips. So it will underflow 2.86 chips. As the Fig.
4-18 shows, lagOV happens 8 times as the phase rotates 8 times. It means that the system has shifted 2.67 chips. The direction of rotation is from S0, to S2, and to S1 counterclockwisely.
All the things are just like we expected.
Chapter 5
Realization of the System on FPGA and PCB
5.1 Realization of the Transceiver
XOR 0
1
TXout mode1
Preamble
Barker Code Counter
CDR
Sequence Detector PISO Get
32
SIPO 32 ΔΣ-DPWM driver 8
RXin
TX RX
Control Data
Driver Signal
Fig. 5-1: Transceiver with backend control circuit
The whole application is shown in Fig. 5-1. The purpose is to use the delta-sigma digital pulse width modulator (ΔΣ-DPWM) to generate PWM signal to control the Power MOS switches. The switches are used to control electric motors, LEDs, or buck converters. The electric motors and LEDs are in open loop control. The buck converters are in closed loop
control. These three components have their own operation frequency. Under this frequency, we can change the on-time duty or PWM of motors or LEDs to control the on-off cycling frequency, on-off duty cycle or dimming. The input of backend control circuit is 32-bit. The data transmission method is through the existing power line on the car to deliver the data. We use DSSS modulation to spread data into chips in order to decrease the noise interference.
Basically a transmitter and a receiver for DSSS are what we need. Therefore, in order to realize this idea, we build a prototype using FPGA and discrete components on a bread board.
XOR
TXout PRBSrst
Barker Coderst
CDR Despread Data
XOR 0
1
TXout mode1
Preamblerst
PRBSrst
Barker Coderst Counter rst
CDR Sequence Detector Get
(a) Test of data recovery
(b) Test of detection of preamble
Fig. 5-2: Test for CDR
As shown in Fig. 5-2, we use the pseudorandom bit sequence (PRBS) encoded by barker code to test whether the CDR can despread the chips correctly. And then, we put the preamble signal before the PRBS data to test the sequence detector. When it receives the recovered data and detects the preamble, it sends out the Get signal to indicate the detection. Besides, we use a single cord wire as the transmission channel.
PRBS input
Recovered data Recovered clock
Fig. 5-3: Test of data recovery
PRBS input
Recovered data Get signal
Fig. 5-4: Test of detection of preamble
Fig. 5-3, 5-4 shows that the system can detect the preamble signal and recover the data correctly. Therefore, the transmitter and receiver can function well.
5.2 SERDES and Backend Control Circuit
Now we add a serializer to the transmitter and a deserializer and the ΔΣ-DPWM control circuit to the receiver, as shown in Fig. 5-5. The simulation procedure is as follows. Set the 32-bit control signal and the transmitter serial out the preamble and the control data. Both of them are encoded by Barker code. Next, the CDR recovers the data and SIPO sends out the 32-bit data in parallel. Finally, the backend control circuit produces the desired PWM control signal. Besides, we use the power line as the transmission channel. Here the DC 12V has not plugged in yet.
TX Control Data RX
Switch
Fig. 5-5: Test of SERDES and backend control circuit
Power line
RX TX
Fig. 5-6: Power line added
(a) On-time 50% (b) PWM 50%
Fig. 5-7: On-time 50% and PWM 50%
(a) On-time 25% (b) PWM 75%
Fig. 5-8: On-time 25% and PWM 75%
(a) On-time 75% (b) PWM 25%
Fig. 5-9: On-time 75% and PWM 25%
Fig. 5-7, 5-8, 5-9 show that the control signals for nMOS switch, we change the on-time
duty and PWM in order to control the LED. The on-time duty allows LEDs to be turn on for 25%, 50% or 75% of a period time. And we can adjust the PWM signal of the on-time, it can change the brightness of LEDs to achieve the function of dimming.
5.3 Coupling Circuit with Power Line
CT CR
RT
VBIAS
LR
VSUP
RLoad
TXout RXin
A B
Fig. 5-10: Coupling circuit with power line
TXout
RXin
A
B
(a) Signals at TXout and A (b) Signals at B and RXin
Fig. 5-11: Recovered PRBS signal
Because the power line is used to transmit the DC 12V supply to every electric appliances on the car. In order to transmit the power and data on the same cable, the inductors and capacitors are used here. We use capacitive coupling to transmit signal. It isolates the output of the FPGA from the direct contact to the large voltage on the cable. So, the common mode level can be different on both sides. The inductor is used to filter out the AC signal which is the transmitted signal on the wire. As L and C form a high-pass filter, the signal on the cable becomes pulse shape. Therefore, we use a Schmitt trigger inverter to recover the
pulse signal. We choose 22μ H of the inductance and 10μ F of the capacitance. Moreover, we bias the other side of the capacitor to move the pulse signal to the common mode of the inverter. Hence the inverter can recover the signal correctly. In addition, we use cement wire-wound resistors to simulate the load current as the real situation.
As shown in Fig. 5-11, the transmitted signal is recovered to the original signal. It means that the front-end circuit can work accurately. Then we transmit the control signal through the channel and the front-end circuit. Fig. 5-12 shows control signal for the nMOS switch.
(a) On-time 50% (b) PWM 50%
Fig. 5-12: On-time 50% and PWM 50%
5.4 Integration of the System
Power Line
AC coupled front-end LED, Motor, Buck converter AC coupled front-end
32 8
Fig. 5-13: System of the application
We build the entire system including the LED, motor, buck converter and control
switches. All of these circuits are realized on the printed circuit boards except for the front-end circuit. For initial test, the power of the LED, motor and buck converter comes from the DC supply separated from the cable. The cable is still connected with the cement wire wound resistors and low DC voltage.
S1P,N
S2P,N
S3P,N
LED Motor
Fig. 5-14: LED, motor, and three pairs of switches
S0P,N
Buck converter Switches
LDO
(a) (b)
Fig. 5-15: Buck converter, LDO, switches for transmitter and buck converter
The low-dropout regulators are used for switches and FPGA board. Because we need 3.3V for both devices, so we can use regulators to generate 3.3V from any voltage and supply current to the devices. After setting up for the test, we adjust the switches to send out the desire control data. Then we test the brightness, on-off duty cycle and on-off frequency of the
LED, and the rotation speed of the motor, and the target voltage of the buck converter.
(a) (b)
Fig. 5-16: Results from buck converter
(a) On-off frequency 3Hz (b) Rotation speed at 80%
Fig. 5-17: Results from LED and motor
We have tape the process of test. These are the pictures derived from video. Fig. 5-16 shows the output voltage of the buck converter, 1.5V and 9V respectively. Fig. 5-17 shows the LED is flashing at 3Hz and motor is rotating at 80% of the full speed.
Final Test
TX RX
DC 12V
Common Ground
Fig. 5-18: Environment of the final test
9-bit Control Switch
TX FPGA
RX FPGA LED, Motor
DC-DC Buck
(a) (b)
Fig. 5-19: Sub-blocks of the final test
Fig. 5-18 shows the environment set up for the final test. We connect the DC 12V supply to the power line as the practical situation. The contact of the receiver end of the cable is used for data receiving and supplies the power for the LEDs, motors and buck converters at the same time. At the transmitter end, we reduce the 32-bit control signal to only 5-bit control code. We list all the conditions for test, and build a look-up table for that. Consequently, we trim the complexity of circuits and wiring. We have demonstrated and taped the data
communication and device control.
(a) VOUT=1.5V of Buck (b) VOUT=3V of Buck
(c) VOUT=5V of Buck (d) VOUT=9V of Buck
Fig. 5-20 Output voltage of the buck converter
(b) Load at 600mA (a) Line from 12V to 5V
Fig. 5-21: Load and line regulation at output voltage 3V
(b) Load at 600mA (a) Line from 12V to 10V
Fig. 5-22: Load and line regulation at output voltage 9V
(c) Dimming of LED at 20% (d) Dimming of LED at 80%
(a) On-time of LED at 20% (b) On-time of LED at 80%
Fig. 5-23: On-time and dimming control of LED
(a) 20% rotation speed of motor (b) 80% rotation speed of motor
Fig. 5-24: Rotation speed of motor
Fig. 5-20 shows the output voltage of the buck converter from 1.5V to 9V. We test the line and load regulation under these voltages. Fig. 5-21 shows the line regulation from 12V to 5V at output voltage 3V. We can see the duty is changed. Fig. 5-22 shows the line regulation from 12V to 10V at output voltage 9V. The duty cycle is changed as well, and load regulation is the same as the one without the load. Fig. 5-23 shows the control of the LED. Fig. 5-24 shows the control of the motor. Table 2.2 is the look-up table of the control functions.
Table 2.2
Con[4:0] function
00000_(0) 1.5V 10000_(16) LED (NMOS) dimming 80%
00001_(1) 3V 10001_(17) LED (NMOS) 6Hz
00010_(2) 5V 10010_(18) LED (NMOS) 3Hz
00011_(3) 9V 10011_(19) LED (NMOS) 1.5Hz
00100_(4) LED (PMOS) dimming 20% 10100_(20) LED (NMOS) 0.75Hz 00101_(5) LED (PMOS) dimming 50% 10101_(21) LED (NMOS) on-time 20%
00110_(6) LED (PMOS) dimming 80% 10110_(22) LED (NMOS) on-time 50%
00111_(7) LED (PMOS) 6Hz 10111_(23) LED (NMOS) on-time 80%
01000_(8) LED (PMOS) 3HZ 11000_(24) Motor (s2) (PMOS= on) (NMOS= off) 01001_(9) LED (PMOS) 1.5Hz 11001_(25) Motor (s3) (PMOS= off) (NMOS= 20%) 01010_(10) LED (PMOS) 0.75Hz 11010_(26) Motor (s3) (PMOS= off) (NMOS= 50%) 01011_(11) LED (PMOS) on-time 20% 11011_(27) Motor (s3) (PMOS= off) (NMOS= 80%) 01100_(12) LED (PMOS) on-time 50% 11100_(28) Motor (s3) (PMOS= on) (NMOS= off) 01101_(13) LED (PMOS) on-time 80% 11101_(29) Motor (s2) (PMOS= off) (NMOS= 20%) 01110_(14) LED (NMOS) dimming 20% 11110_(30) Motor (s2) (PMOS= off) (NMOS= 50%) 01111_(15) LED (NMOS) dimming 50% 11111_(31) Motor (s2) (PMOS= off) (NMOS= 80%)
Chapter 6
Conclusion
In this thesis we have proposed a data communication method with power line. We use DC 12V power line of the automobile as the transmission media. We apply the capacitive coupling to transmit and receive the data signal. We can expect that the signal will be corrupted by various noises existing in the channel. So we use direct sequence spread spectrum (DSSS) modulation technique to encode the control data. We have designed a DSSS transceiver to perform the function of spreading and despreading. We choose 11-bit Barker code which is also used in 802.11 wireless communications as the spreading sequence. We have designed a clock and data recovery circuit which combines the phase picking for clock recovery and byte synchronization for data recovery. We utilize the shifting of three phases of the clock to achieve 1/3 chip time delay which is enough for code acquisition. We use a pair of early and late phases to track the frequency error between transmitter (TX) and receiver
(RX), and a digital loop filter is used to filter out the high frequency noise or jitter. The 32-bit SERDES and backend control circuit are realized to perform the serial transmission and PWM control of LED, motor and buck converter. Finally, we use FPGA and PCB to realize the whole system with power line. We have demonstrated and taped the data transmission and controlling of the devices. We have proved the idea of power line communication for automotive electronics is feasible.
The following is the specification table for the DSSS transceiver. The three oversampling phases are generated from the global clock of the FPGA. For consideration of measurement, we lower the chip rate and the data rate to ease requirement of the front-end circuit.
Table 2.3 Specification for the DSSS transceiver
Burst-data length 75 bit
FPGA global clock 50MHz
PN code 11-chip Barker code
Chip rate 260KHz
Data rate 23.67KHz
Counter size N 3 (continuous type)
Inductor (front-end) 22μ H
Capacitor (front-end) 10μ F
Bibliography
[1] Michael Perrott, “High Speed Communication Circuits and Systems,”
MITopencourseware, Massachusetts Institute of Technology, Boston, MA, United States, 2003.
[2] S.C. Hsu, “Study and FPGA Implementation of Powerline Communication System using OFDM signals,” M.S. Dissertation, Department of Electrical Engineering, National Cheng Kung University, Taiwan, June 2004.
[3] Y.L. Peng, “Implementation of a Power Line Modem Using PFDM Technique,” M.S.
Dissertation, Department of Electrical Engineering, National Cheng Kung University, Taiwan, June 2002.
[4] H.Y. Chiu, “Adaptive Bit and Power Allocation for OFDM under Power-Line Channels,” M.S. Dissertation, Department of Electrical Engineering, National Cheng Kung University, Taiwan, June 2005.
[5] K.L. Hsiao, “A Small Area Low Power 2.5Gb/s Transceiver with Digitized Architecture,” M.S. Dissertation, Department of Electrical and Control Engineering, National Chiao Tung University, Taiwan, July 2006.
[6] C.H. Lee, “All Digital Clock and Data Recovery Circuit Architecture for High Speed Serial Link,” M.S. Dissertation, Department of Electrical Engineering, National
[6] C.H. Lee, “All Digital Clock and Data Recovery Circuit Architecture for High Speed Serial Link,” M.S. Dissertation, Department of Electrical Engineering, National