Background…

The progress of research into integrated circuits (ICs) is focused mainly on two goals: (1) increasing circuit performance (mainly by increasing circuit speed) and (2) increasing the functional complexity of the circuits. Scaling down device sizes is considered a very effective means of achieving these goals, but discovering technologies for achieving sub-60-nm contact holes is still a challenge [1]-[2].

The ITRS 2002 Update predicts that, for ASIC fabrication, the critical dimensions (CDs) for contact holes after etching will be required to be 65 and 45 nm by 2007 and 2010, respectively. Technologies that use chemical shrinkage for patterning sub-100-nm contact holes in resists have been reported previously [3]. In that report, the authors proposed using a polymeric shrinking agent that cross-links on the pattern’s sidewalls at a suitable mixing-bake temperature, but such a shrinkage technique faces the problem of defect formation in the resist pattern at higher mixing-baking temperature. Therefore, such chemical shrinkage technology has not been used previously for the generation of sub-60-nm features. Solving this problem, and to achieve the goal of preparing sub-60-nm contact holes in a silicon dioxide layer, requires controlling the shrinkage temperature for the ca. 90-nm contact holes in the resist and improving the etch process that allows further shrinkage to occur.

During the past two decades, there has been an extremely rapid growth in both the technology and the application of microelectronics, to the point that it now pervades virtually all aspects of commercial and military business. The size and performance of microelectronic devices has been improved substantially, especially in the past few years [4]-[5]. In the updated International Technology Roadmap for

Semiconductors, the 50 nm contact hole in the resist will be used in year 2011. The electron beam direct writing (EBDW), in comparison with optical lithography, is a promising means for controlling and patterning small features, down to sub-100nm [6]. This technology has a cost advantage for production volumes below 100 lots in the future [6]. In EBDW, the Gaussian beam has better resolution than shaped beam.

But, the shaped beam has an at least 10-fold higher throughput than Gaussian beam due to imposing several pixels per shot [7]. In order to achieve the better resolution and high throughput for shaped beam technology, the utilization of thin resist film is inevitable [8]. However, the thin resist will face the challenge of poor etching resistance and serious line edge roughness. Nano-scale molecules are the possible means to solve the unaffordable etching resistance and enhance the lithographic performance for the thin resist film generation.

In the last few years, the industries focus on the planar CMOS scaling. However, scaling planar CMOS to short gate length will face many problems like electrostatics, excessive leakages, and mobility degradation. Non-planar CMOS MOSFETs provide potential advantages in packaging density, carrier transport, and device scalability [9].

SOI FinFETs technology has a lot of advantages such as the reduction of parasitic capacitances, the feasibility of diffusion resistors and capacitors free of junction effects, better device isolation leading to absence of latch up, substrate coupling and good gate control ability. But the floating body effect is a main problem of the SOI MOSFET devices. It will cause drain current “kink”, abnormal subthreshold slope, and low breakdown voltage [10]-[11]. The metal salicidation method has been used to suppress the floating body effect and DIBL [12]-[13] and reduce parasitic S/D resistances in the thin-film SOI devices.

Silicon technology has formed the basis of microelectronics and electronics systems for more than 30 years. In terms of productivity, the density of devices on a

silicon chip has followed Moore’s law, doubling about every two or three years since about 1980. Many researchers are interested in scaling down electronics devices so that they may perform at higher speeds and be prepared at lower costs. Conventional SiO2 gate dielectrics are reaching their physical thickness limit (1.5 nm); they cannot be used as CMOS devices because the high direct tunneling current and poor reliability. For further scaling of devices, it has been proposed that SiO2 be replaced by high-k dielectric constant materials, such as ZrO₂, HfO₂, Ta₂O₅, Al₂O₃, TiO₂, and silicates (ZrSixOy and HfSixOy) [14]–[21]. In fact, dielectric films having higher permittivity allow the use of thicker films of equivalent electrical thickness as silicon dioxide; this situation will reduce the leakage current and improve the reliability of the dielectric films.

The most important properties of high-k dielectric materials that are necessary to maintain continuous increases in device performance and density are their low leakage current, low equivalent oxide thickness (EOT), high breakdown strength, high thermal stability, and gate electrode compatibility. The EOT, t_eq, of an alternative high-k dielectric employ can be obtained from the simple equation

t_eq = (K_ox / K_high-k) t_high-k.

Where Kox and Khigh-k are the dielectric constants of silicon oxide and the high-k dielectric, respectively, and t_high-k is the physical thickness of the high-k material.

Future downscaling will require high-k materials in which EOT values are reduced to nearly 0.7 nm [22]. We must bear in mind that many of the characteristics of these high-k dielectrics—such as their breakdown mechanism and hysteresis phenomena—are quite different from those of conventional silicon dioxide. When the gate dielectric materials experience high-temperature conditions (> 800 °C), the thermal stability of the high-k dielectric on silicon is an important issue that must be addressed for future MOSFET devices. The most suitable range of dielectric constants

is between 20 and 40. If the material has an extremely high k-value (> 80), it will induce a large fringing effect. For the purposes of achieving a low leakage current, it is desirable to choose a dielectric material that possesses a large band gap energy and a large band offset with respect to the Si substrate. ZrO2 has a dielectric constant of 25, a wide band gap, good thermal stability, a high hardness, a high melting point, chemical hardness, and a high refractive index.

Recently, numerous technologies have been developed for the preparation of various high-k films [23]-[25]. To prepare insulating thin films, atomic layer deposition (ALD), physical vapor deposition (PVD), and chemical vapor deposition (CVD) methods have all been used to prepare films for new technologies. In the ALD process, ZrCl₄ and H₂O are used to prepare the ZrO₂ films. For the PVD process, a zirconium metal target is used for sputtering under ambient oxygen to deposit the ZrO₂ films. In the CVD method, ZrCl₄ precursor is used to deposit ZrO₂ films. The sol–gel method is a very interesting simple technique for preparing ceramic films [27]-[31].