C HANNEL A NALYSIS

Concern about the performance of wires in scaled technologies has led to research exploring other communication methods[15]. The relationship between wires and gate delays has many interesting problems. So understanding the wires is the first course to research the high-speed links.

In our design, the system transmission line model is fixed. However, we must account for its characteristics in our signaling system. The channel is the entire path from the output of the transmitter circuit to the input of the receiver circuit. This includes the connections from the die input and output pads to the package pin on both sides and the PCB trace that connects them. The termination resistor which matches the characteristic impedance of the channel is used to minimize the signal reflection. After the transmitter circuit lunches a signal, the signal run through the pad, bonding wire, package pin, PCB trace, and the receiver package. As we know, a signal can continue to propagate along a transmission line as long as the impedance remains constant. Changes in the impedance along the line will cause part of the signal energy be reflected which then propagates in the opposite direction (back toward the

transmitter). If the signal is reflected again, the second reflection would interfere with the signal that is transmitted after the roundtrip propagation delay. It appears as signal pattern-dependent noise. A common source of impedance mismatch is discontinuities between the chip package and PCB trace.

Consequently, the package parasites should be taken into account in the design of high speed interface circuits from very beginning. Thus, simulations must include a reasonable circuit model of the package and the transmission line model of PCB trace.

Figure 2.5 illustrates the channel model that includes termination resistors and packaging parasitic.

In the following sections, we will identify the parasitic parameters of the package and build the equivalent transmission line model for the PCB trace between chips.

Tx

R_term R_term

L_bond

C_pad C_pin

W element L_bond

L_bond

Tx L_bond

L_bond

Figure 2.5 The channel model that includes termination resistors and packaging parasitic

2.3.1 Channel Medium

PC board traces and coaxial, twisted-pair cables behave as transmission lines that store and propagate signal energy. These lines can be modeled by a series of lumped LCRG elements as shown in Figure 2.6. The loss in transmission is primary due to the series resistive component of the copper (R) and parallel conductive component of the dielectric (G).

L R

G C

Figure 2.6 Lumped LCRG model of a transmission line

The major frequency-dependent loss in many electrical link using conductors is due to skin-effect resistance. This effect can be modeled as an increase in the series resistance of the wire as shown in Figure 2.6. Higher frequency signals propagate closer to the surface of the conductor. The resulting signal current conducts within a limited depth, the skin depth, on the conductor surface, which is defined as [16] (3).

0

δ = 1

π× µ × f ρ

, (3)

where ρ is the resistivity of the conductor, and f is the frequency of the signal.

Hence, the effective series resistance (R_skin) of the cable corresponding to this depth increase with square root frequency [17] :

^⋅ ⋅

for a round conductor with radius r. This relation shows a frequency dependent resistive loss. Note that the above equation is valid only for frequencies well above the skin frequency, f_skin, where the skin depth is smaller than the radius of the wire:

(

^{⋅ ⋅}

)

skin

f = ρ

π µ r . (5)

With some insulating materials, dielectric absorption also causes frequency dependent attenuation. This loss can be modeled as a conductance G between the signal wire and ground. This effect can be mitigated by using a low-loss dielectric material. However, because of certain restrictions on PC board materials, the choice of dielectric is limited. PCB trace usually demonstrates a considerably higher dielectric loss compared to cables. Dielectric loss for each material is usually

expressed in terms of a parameter, called the loss tangent defined as (6).

where C is the capacitance per unit length as shown in Figure 2.6. This quantity is approximately constant with frequency. The dielectric loss, G, typically increases linearly with frequency. Base on the above equations, the approximate cable frequency response in dB accounting for both skin effect and dielectric loss is given by[13] (7), where l is the length of the cable, h and s h are the skin effect and _d dielectric loss coefficients respectively. h is usually larger than_s h , so dielectric loss _d may be neglected. On the other hand, for the PCB trace, h is marginally larger _s thanh , so it needs to be considered. _d

(

^{s⋅ d⋅}

)

^⋅

H(f,l) = - hdB f + h f l . (7)

2.3.2 Characteristic Impedance of the Channel

The characteristic impedance Z of the transmission line is defined by the ₀ ratio of the voltage and current waves at any point of the line; thus, V I = Z . Figure ₀ 2.7 shows the equivalent electric circuit of such a line segment. The quantities ^{v z t}

( )

^,

and ^{v z + ∆z,t}

( )

denote the instantaneous voltages at z and z + ∆z respectively.

Similarly, ^{i z,t}

( )

^{and i z + ∆z,t}

( )

denote the instantaneous currents at z and z + ∆z , respectively. Applying Kirchhoff’s voltage law, we obtain[18]

( )

^{− ⋅}

( )

^{− ⋅∂}

( ) (

⁻

)

Similarly, applying Kirchhoff’s current law to the node N in Figure 2.7, we have (10) by the same method above.

₋^∂

( )

_{= ⋅}

( )

₊ ^∂

( )

∂ ∂

v z,t i z,t

R i z,t L

z t . (10)

(9) and (10) are a pair of first-order partial differential equations in ^{v z,t}

( )

^and

( )

i z,t . They are the general transmission-line equation (PDE). For harmonic time dependent, the use of phasors simplifies the transmission-line equations to ordinary differential equations (ODE).

R ∆z L ∆z

Figure 2.7 Equivalent circuit of a differential length of a two-conductor T-line For a cosine reference we write

( ) ( )

where phasors V(z) and I(z) are functions of the space coordinate z only and both may be complex. Substitution of (11) in (9) and (10) yields the following differential equations for phasors V(z) and I(z):

( ) ( )

(12) are coupled time-harmonic transmission-line equation. They can be combined to solve for V(z) and I(z). We obtain the following one-dimensional second-order ordinary differential equations(13).

2 2 is the propagation constant whose real and imaginary part α and β, are the

attenuation constant (Np/m) and phase constant (rad/m) of the line, respectively.

We already derived the governing equations(13) for time harmonic V(z) and I(z) on a transmission line. Let us now examine their characteristic on an infinite line. The solutions of (13) are

( ) ( )

where the plus and minus superscripts denote waves traveling in the +z- and –z-direction, respectively. Wave amplitude

(

V ,I0⁺ 0⁺

)

and

(

V ,I are related by 0^- 0^-

)

(12), and we can verify that the relation

+

For a infinite line (actually a semi-infinite line with the source at the left end) the terms containing the e^{γ z⋅} factor must vanish. If not, these terms would increase indefinitely with z, a physical impossibility. There are no reflected waves; only the waves traveling in the z+-direction exist. Thus[18, 19]

,

The ratio of the voltage and current at any z for an infinitely long line,

+ + + +

0 0

V (z) I (z)= V I , is independent of z and is called characteristic impedance of the line.

0

( )

R+ jωL γ R+ jωL

Z = = = Ω

γ G + jωC G + jωC (18)

Note that γ and Z₀ are characteristic properties of a transmission line whether or not the line is infinitely long. They depend on R, L, G, C and ω but not on the length of the line. An infinite line simply implies that there are no reflected waves[19].

2.3.3 SPICE Model of the Channel (PCB Trace)

In inter-chip communication system, the signaling media is usually the printed circuit board (PCB) or multi-chip module (MCM) traces. In terms of circuit simulations, the problem is how to model the traces for high speed transmission. The response of any conductors to an incoming signal depends greatly on the effective length of the fastest electrical feature in the signal. The effective length of the signal’s rising edge is[16]

T^r

= D

l , (19)

where l is the effective length of the rising edge in. Tr is the rise time of the signal in ps, and D is the propagation delay of the conductors in ps/inch.

For example, in the 2.5 Gbps serial link, the rise time of the bit cell is often 100ps ~ 200ps. For transmitter design, the rise time is usually controlled to be around 1/4 ~ 1/2 of the bit time. Considering the worst case, when the rising edge propagates along a microstrip of the FR4 board, it has an effective length of 0.56 inch. For our system, the trace length is considered to less than 21 inch on the board. Evidently, the potential of the signal pulse propagates along the trace is not uniform at all points.

This type of system is called a distributed system. A rule of thumb is that the circuit behaves mostly in a distributed fashion when the wire is longer than one-sixth of the effective length of the rising edges[16].

The metal in a typical PCB board is usually copper and the dielectric is FR4, a type of fiberglass. The two most common types of transmission lines are micro-strips

and strip-lines. In our design, we use the microstrip for simplicity. Its simple structure is shown in Figure 2.8, and the corresponding formula is shown in (20)[18, 20].

^{≅ ⎛}_⎜ ^⎞_⎟

( )

⎝ ⎠

0 r

r

87 5.98H

Z ln Ohms

0.8W +T ε +1.41

(Valid when 0.1<W/H < 2 and 1< ε < 15)

(20)

T

W

H ε_r

T

W

H ε_r

Figure 2.8 Characteristic impedance approximations for microstrip line The SPICE Devices Models Manual [20] presents the method to describe a transmission line. After we run the HSPICE, the output shows six parameters, L, C, R0, G0, RS, and GD, which RS is the skin effect parameter in(Ω/m Hz), G0 is the DC conductance of the dielectric material in S/m, and GD is the dielectric loss parameter in(S/m Hz⋅ ).

Chapter 3

2.5Gbps LVDS Transmitter with SSN Reduction

3.1 Simultaneous Switching Noise Rejection

Simultaneous switching noise (SSN) or ground bounce caused by many electrical and packaging properties. SSN become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex due to the thousands of interconnects that need to be analyzed [21, 22]. Today, many SSN analyses are studied in different fields.

Output pad driver is the main source of the SSN because of the large transient currents during switching. SSN may even appear at low operation frequency signal that has sharp transition. The peak of SSN usually occurs in the beginning of

transition. Different pad and package structures will have different value of parasitic inductance and capacitance. Hence, the design must be careful here.

SSN or ground bounce depends on many electrical and packaging properties relate to each other. In general, the same phenomenon applicable to power is called VDD bounce. Both ground bounce and VDD bounce are important noise source. Since devices near the high-voltage level tend to have more noise margin than those in the low-voltage level. Therefore, ground bounce is considered more often. The SSN might still be low if a large number of supply bonds are used. For low SSN digital system designs, we must take all the relevant parameters into account and try to find the most effective approaches to reduce the SSN. In this section, we will discuss some techniques for the SSN reduction. Before that, we calculate the amounts of SSN noise firstly.

L_bond

C_pad C_L

VDD

C_vdd L_vdd

C_gnd L_gnd

input signal

X

Figure 3.1 Simplified electrical model of chip-package interface

The last stage of output buffer is the main source to generate SSN during transient because of its high driving capability. Therefore, we focus the analysis of

SSN caused by the last stage of the buffer in this section. Conventionally, Shockley’s square law model is used in the analysis of MOSFET circuits due to its simple close-form equation. However, when excluding the velocity saturation effects in sub-micron technologies, the Shockley model can not regenerate the voltage-current characteristics of the short-channel MOSFET transistors. Therefore, alpha-power law MOSFET model[23] that include the velocity saturation effects is used here. Using alpha-power law MOSFET model, the drain current of MOSFET is given as

( )

where k is drivability factor, VTH is the threshold voltage, α is velocity saturation index, and V’D0 is the drain saturation voltage. Typical values of α range from 1.0 to 1.3 for NMOS transistor.

When the output changes from high to low, because of the velocity saturation effects, the NMOS transistors usually stays in the saturation region during the time of input signal transient. It can be well assumed that when the ramp input signal (Vin) reaches VDD, SSN reaches the maximum value. For n output drivers which share the common ground line switches simultaneously, the discharging current flow through the Lgnd is given in[24]

i(t)= n i (t)= n k V (t)-V (t)-V^⋅d ^⋅ sn

(

in n tn

)

^αn, (22) the switching noise (VX) that is the voltage built up in node X in Figure 3.1 can be

written as

^⎡_⎣

(

in n tn

)

DD^⎤_⎦^αn DD^αn t

n sn gnd

V (t)-V (t)-V V V t - t

V (t) = 2nk L (24)

Take the power series of ^⎡_⎣

(

V -V -Vin n tn

)

VDD^⎤_⎦^αn and neglect terms with order higher than two, we can obtain a close-form equation as follows

( )

The Vn,max estimated by (27) and other predict equations together with SPICE simulation results are similar. The error as compared with SPICE is below 5%. Note that, due to the negative feedback effect of Lgnd, the noise is not a linear function of the number of the drivers.

This is the analysis and calculation of the SSN. Next, we discuss some techniques that reduce SSN[24].

3.1.1 Optimal Rise/Fall Time

In the sub-nanosecond region, unnecessarily fast rise/fall edges of pulses should be avoided in order to achieve low SSN. An optimal size of drivers can be estimated in terms of required rise/fall time, loading, and pulse swing. Many semiconductor foundries offer ASIC designers a variety of I/O buffer cells, from 2mA to 24mA in both non-slew rates controlled and slew rate controlled for different requirements.

These buffers should be carefully chosen to be just enough for the specification.

It is the edge rate not the frequency that affects the ground bounce. The slew rate dV/dt of the output significantly affects ground bounce more than any other parameter. The slower the output slew, the lower the ground bounce will be. It

becomes a trade off between performance and signal integrity. But this is not the best way to solve the SSN problems.

3.1.2 Reducing Inductance

Zero inductance in the power supply network results in zero SSN. Since the parasitic inductance is mainly related to packaging, e.g. wire-bonds, or package. It leads using advanced packaging techniques, such as ball-grid arrays (BGA) packages and multi-chip module (MCM) substrates with full supply planes, or flip-chip on a MCM will certainly reduce SSN. In addition, the arrangement of supply paths has a strong influence on SSN since switching noise is directly caused by the effective inductance of the power supply networks.

3.1.3 Reducing Signal Swing and Use Differential Drivers

A small signal swing leads to a low SSN. Since a significant part of the SSN is generated by large output buffers, the use of LVDS outputs instead of full swing CMOS outputs reduces SSN. The LVDS technique has already been widely used in many high-speed IC chips using BiCMOS as well as CMOS technologies. The drawback of reduced noise susceptibility with reduced swing signals is improved by using differential signals, with which common mode noise is effectively rejected.

Moreover, differential outputs into impedance matched and coupled differential lines result in reduced overall noise generation and increased noise immunity. However, steady-state power consumption is the side effect because of the constant current sink through the termination resistors.

3.1.4 Separate Power Supply Network

Since SSN is mainly generated by large bus/clock drivers and output buffers, it should be regarded as a design rule to separate the supple for internal logics from the supply for output drivers, especially when many of them switch simultaneously.

Power supply planes on an MCM substrate might be split into several parts in order to eliminate noise coupling between different chips or different functional blocks.

However, the potential stability problem at system level requires a common ground plane on the PCB that supports chips and MCM modules.

3.1.5 Decoupling Capacitors

In MCM and advanced PCB designs, metal planes are used for the power supply and ground. Although the inductance of these planes is small, the inductance associated with vias and bonding leads (or wires) from an MCM substrate to a board (or package) is often considerable. If meshed supply planes are used, the inductance is not negligible, especially at high speeds. This is because the supply or return current paths are strongly influenced by the meshed planes. To use decoupling capacitors effectively, they have to be mounted with multiple-vias close to the chip being concerned to reduce parasitic inductance. Surface-mounted capacitors with large capacitance values (e.g. > 100nF) have large parasitic inductance. Therefore, it is preferable to use medium value capacitors (~1-10nF) with a high self-resonance frequency and a high Q value. An important note here is to distribute them over the entire module. Capacitors formed between two closely placed power and ground planes on an MCM or PCB provide high-quality decoupling with a very low parasitic inductance.

Besides, varying the capacitive load has an effect on both the amplitude and the width of the pulse. The amplitude tended to decrease with increasing capacitive load, whereas the pulse width increases. The increased capacitive load tends to reduce the slew rate on the outputs, thereby, reduce the amplitude.

3.2 Transmitter Architecture

The proposed transmitter overall architecture contains a single to differential buffer, a controlled predriver module, a fixed LVDS driver, and a programmable LVDS driver. In Figure 3.2, the first buffer converts the single ended data input to differential. The upper signal path is for the fixed driver and the lower one is for the programmable driver. The upper signals pass to the first six orderly turn-on buffers

blocks. Note that, the signals are duty cycle controlled to reduce SSN as well. Besides, because of the process variation or layout mismatch, the output level is not guaranteed to have an expected voltage level. So the additional controllable LVDS drivers can enhance the output driver current to compensate the output voltage swing through the programmable LVDS driver as in Figure 3.2.

Orderly

Figure 3.2 The overall transmitter architecture

The orderly turn-on block converts one differential pair signals to six. All the six differential pairs go through the duty cycle modulation block independently.

Finally, the signals turn on the gate of the drivers “orderly”. On the other hand, the control logic decides whether the signals pass or not. Base on the PMOS and NMOS driver capability, the number of the compensated driver can determine by outside control signals.

3.3 System Components

3.3.1 Orderly Turn-On Buffer

The idea of the orderly turn-on buffer is shown in Figure 3.3. The conventional driver has a current spike as shown in the figure. But by our orderly turn-on architecture, the dI/dt is decrease a lot compare to conventional one. The big driver is divided into several small drivers as the figure shows. All small drivers drive the load one by one between a little time interval. The influence by this circuit is that the slew rate is slowed down and the dI/dt curve also reduces.

Driver di/dt curve Driver di/dt curve

conventional conventional Orderly turned Orderly turned--onon

Orderly rising signal

Orderly turned--onon

Orderly rising signal

Figure 3.3 The idea of the orderly turn-on buufer

It is very difficult to generate a series of signals whose intervals are less than ten picoseconds. For TSMC 0.18-um technology, the gate delay of the inverter is at least 20 ~ 30 picoseconds. Even using differential pair inverter approach, we can just suppress the gate delay to about 20 picoseconds. In the 2.5 Gbps transmitter design, to maintain the stable quality of eye-diagram, the rising and falling time should not be longer than 100 picoseconds. Since there are thirteen PMOS or NMOS need to be

turned on in the worst case. The intervals between each signal can not be longer than 15 picoseconds. Therefore, how to design a small delay circuit is a very challenging issue.

Figure 3.4 Orderly turn-on buffers

Some technologies suppress the SSN by separating the gate signal[25]. But the

Some technologies suppress the SSN by separating the gate signal[25]. But the

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