CHAPTER 4 A SERIAL-ATA DRIVER WITH OUTPUT
4.3 B UILDING B LOCKS
4.3.1 Counter
The counter is the first simple block. The counter operation speed is as low as kHz. So we choose the simple architecture shown in Figure 4.2. There are six JK Flip-Flops and a NOR gate. All J and K are connected to power supply so the JK Flip-Flops become T-Flip-Flops. When the clock trigger, S1~S6 trigger in sequence.
The Tx signal is LOW and S6 is HIGH initially. When the S5 trigger the NOR gate, S6 fall to LOW and trigger the last JK Flip-Flop. The Tx signal rising and set the one input (Tx signal) of the NOR gate to HIGH. So make the S6 always LOW (stable) to hold the Tx signal steady until the reset signal.
J
reset reset reset reset reset reset
S6
Figure 4.2 The architecture of the counter
Figure 4.3 shows the function verification of the counter above. After the reset, S1~S5 begin to count until S6 changes. Tx signal rise from LOW to HIGH and hold on until the next reset. We use this counter to decide when the transmitter to transmit or do self-calibration. Tx signal presents the operation mode of the SATA transmitter.
S1
Figure 4.3 The function verification of the counter
4.3.2 Finite State Machine (FSM)
The finite state machine (FSM) decides the strength of the compensated output drivers. The S0~S7 connect to the gate of the driver to turn on or off the transistors.
The FSM function like a bidirectional shifter. When the up or down signal (the two signal are always complementary) changes, S0~S7 will shift left or right depend on the up signal is HIGH or LOW. The up signal decides the multiplexer and the shift takes place when enable signal is triggered. The enable signal is the AND of the clock, txb and the EXOR of “up” and “down”. Therefore, we can ensure that the shifter synchronizes with the clock and txb.
S3 S4 S5 S6 S7
Mux Mux Mux Mux Mux Mux Mux
clk
Mux MuxMux MuxMux MuxMux MuxMux MuxMux MuxMux
clk
enable
txb
Figure 4.4 The Finite State Machine (FSM) in our transmitter.
We connect the first and last multiplexer to the power supply and ground because we need the code shift like Table 4-1. For example, if the initial value of the shifter outputs (S0~S7) are all zero, S0 will be high when a right shift command occur.
On the other hand, when we shift left, the state value will be low from S7 to S0 one by one. If we continue shift right many times, all state value are high. But when a shift left command occurs, S7 must be zero. That is why we use the power supply and ground to replace the vacant input of the first and last multiplexer.
Table 4-1 An example of the FSM code S0 S1 S2 S3 S4 S5 S6 S7
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Shift
Right
Shift Left
The flip-flop of the finite state machine is of the static type. We can not use the dynamic flip-flop, because after the self-calibration the output value of the D flip-flop must hold on itself forever.
4.3.3 Digital Control Circuit and Comparator
The digital control circuit and comparation circuit will be described in this section. The source information of the FSM is from the comparators and the digital control circuit. As shown in Figure 4.5, we use a simple two-stage operational amplifier (OpAmp) to compare the output voltage and reference voltages. Because the output is digital type, we neglect the stability of the OpAmp and add some inverters to drive the signal to digital control block.
VREF VIN
OUTPUT VDD
Figure 4.5 The comparator circuit design in this application
After the comparison with output voltage level and reference voltage, we have four digital outputs. In Figure 4.6, VHIGH and VLOW connect to two comparators. The outputs (A, B, C, D) will have nine cases instead of sixteen because the (A, B) and (C, D) will not have “10” output. To use the four outputs to decide the FSM to shift left or right, we follow the table (iii) in the figure. The minterm list can be achieved by a circuit design. They are just inverter and transmission gate like (iv) in the figure.
Finally, the output Up/Down are the input of the FSMs.
FSM
0000 0000 1111 1111 0000 1111 0000 1111 0011 0011 0011 0011 0101 0101 0101 0101
up / down = B / A
Figure 4.6 Function and design flow of the digital control circuit
4.3.4 SATA Driver
The transmitter in this chapter is for Serial ATA. The Serial ATA is established by several companies such as Dell, and Intel …etc. The SATA 1.0a specification shows the reference transmitter circuit example as in Figure 4.7. Notice that pass gate impedance plus resistor should be set to 50Ω. We design the circuit level like the right side of the figure. The four switches can be controlled to be 50Ω by our digitized driver. Due to the switches are all 50Ω ideally, the output high would be 375mV and output low be 125mV by voltage divider. So the differential output should be 250mV as SATA specification provide.
Like the previous LVDS driver, because we removed the two current sources, we will face the SSN consequences. So the SSN rejection circuit will be added in this SATA driver. The duty cycle modulation must be modified because the switches are all NMOS instead of CMOS in LVDS switches. The control signals have to be taken care to avoid functional error.
500mV
-SATA 1.0a Specification
50Ω
-SATA 1.0a Specification
50Ω 50Ω
Figure 4.7 The transmitter circuit example in SATA 1.0a specification