The worst simulation result of different delay compensation is shown in Fig. 5.13.
Comparing with system level simulation, the main difference is that the non-delay architecture in circuit implementation has a signal dependent delay to degrade the SNR performance.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
10 15 60
55
50
45
40
20 25 30 35
SNDR [dB]
RC var.=0%
RC var.=+-10%
RC var.=+-20%
RC var.=+-30%
Loop delay [Ts]
Figure 5.13 Worst case of RC-variations influence on 3rd order ΣΔ with different delay in circuit level simulation
The circuit simulation with different corner and temperature are shown in Fig.
5.14 and Fig. 5.15. architecture is found th
performance with lower design requirements of amplifiers. We could note that a ΣΔ modulator with less delay compensation is more robust and stable in process and temperature variations.
The less delay at has better system
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 42
44 46 48 50 52 54 56 58 60 62
TT FF SF FS SS
Loop delay
NDR S
Figure 5.14 SPICE corner simulation
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
48 50 52 54 56 58 60 62
SNDR
Temp.=0 Temp.=25 Temp.=50
Loop delay
Figure 5.15 Temperature simulation
The third order ΣΔ modulator with quarter delay feedback was designed in 1P6M MIM standard process. The core chip layout is shown in Fig.
TSMC 0.18um
5.16. To prevent the substrate noise from coupling each other, the analog and digital parts are separated and surrounded by the clean guard rings. The layout of the integrators and comparators is symmetry for balancing the differential signal paths.
The core area of the chip is 220×200μm2.
capacitors
opamps resistors
bias
quantizer
Digital part
Figure 5.16 Chip layout of a third order ΣΔ modulator
Fig. 5.17 depicts the simulation output PSD for low and high signal frequencies (42-KHz and 1.2-MHz) at input level of -7dB respectively. The full-scale signal 0 dB refers to a sine wave at the input with 1.8pp. The behavior is almost the same for low and high input frequencies (both SNDR equal about 60dB). For large input
amplitudes, the distortio apidly. When the input
signa
n due to the integrators increases r
l exceeds the reference voltage, the ADC is overloaded and the performance is degraded. Fig. 5.18 shows SNDR versus the normalized input levels as a function of
input signal amplitude. Table 5.4 shows a summary of the performance.
103 104 105 106 107 108
-140 -120 -100 -80 -60 -40 -20 0
Y[k] dB
The FFT of Y[n] The FFT of Y[n]
103 104
105 106
107 108 -140
-120 -100 -80 -60 0
Freq
-40 -20
Freq
Y[k] dB
Figure 5.17 (a) PSD at fi=42.72-KHz (b) PSD at fi=1.2-MHz
Figure 5.18 SNDRs versus input signal Table 5.4 Performance Summary
Technology 1.8V / 0.18um
Signal Bandwidth 2MHz
OSR 25
Peak SNDR 62dB
Dynamic Range 64dB
Power consumption 6.5mW@VDD=1.8v
Chapter 6 Conclusion
With the rapid growth in portable electronic market, integrating the digital and analog circuits on a single chip at low supply voltage will be an indispensable trend in the future. The C
system. Due to their low sensitivity to th ponents, they are suitable for being utilized to implement the high speed and medium resolution.
In this thesis, different loop delay compensation effect on a CT ΣΔ modulator was explained. It’s worth mentioning that using higher quantizer sampling rate at feedback latches could produce different numbers of digital feedback delay. In this design, we used feedback latches with two times of quantizer sampling rate to produce quarter delay timing.
Different classes of CT ΣΔ modulators with different delay compensation were discussed in this thesis. Process variations alter the NTF, which alter NP and lower
the effective SNR. The re rapidly poles move
toward the unit circle fro aracteristic is proved in
PG or pole locations, this thesis proves that a ΣΔ modulator with less delay compensation is more robust and stable in process variations.
This thesis proves the property not only on mathem theorems, but also proves it on practical circuit A third order CT odulator with active-RC integrators has been .18μm TSMC CMOS process. The coefficients of the modulator were calculated by using the echnique.
T ΣΔ modulators are popularly used in modern communication e analog com
G longer loop delay compensation, the mo
m original pole locations. The ch N
atic
implements. ΣΔ m
accomplished in 0
modified-z-transform t
References
[1] S. R. Rorsworthy, R. Schr
ma Data Converters,
Piscataway, NJ:IEEE Press [2]
ireless Applications,”
[5]
, vol.
/D Conversion in Radio Receivers, 2001.
eier, and G. Temes, Delta-sig , 1997.
P..Benabes, M.Keramat and R. Kielbasa, “A Methodology for designing continuous-time sigma-delta modulators” European Design and Test
Conference (ED&TC 97), pp. 46-50, Paris, 1997.
[3] M.S. Kappes, “A 2.2-mW CMOS Bandpass Continuous-Time Multibit Δ-Σ ADC with 68 dB of Dynamic Range and 1-MHz Bandwidth for W
IEEE J. Solid-State Circuits, Vol. 38, pp. 1098-1104, July 2003.
[4] M. Moyal, M. Groepl, H.Werker, G.Mitteregger, and J. Schambacher, “A 700/900 mW/channel CMOS dual analog front-end IC for VDSL with
integrated 11.5/14.5 dBm line drivers,” in IEEE ISSCC Dig. Tech.Papers, 2003, pp. 416–504.
S. Yan and E. Sánchez-Sinencio, “A continuous-time ΣΔ modulator with 88 dB dynamic range and 1.1 MHz signal bandwidth,” in IEEE ISSCC Dig. Tech.
Papers, Feb. 2003, vol. 46, pp. 62–63
[6] S. Paton, A. Di Giandomenico, L. Hernández, A. Wiesbauer,Potscher, and M.
Clara, “A70-mW 300-MHz CMOS continuous-time sigma-delta ADC with 15-MHz bandwidth and 11-bits of resolution,” IEEE J. Solid-State Circuits 39, no. 7, pp. 1056–1062, Jul. 2004.
[7] J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for
High-Speed A/D Conversion, 2000.
[8] L . Breems and J.H. Huising, Continuous-Time Sigma-Delta Modulation for A
[9] Buhmann, A.; Keller, M.; F.; Manoli,
Y.;“ Time-Continuous Del s: From Theory to Practical
a ,
th
,
z Kuttner, Patrizia Greco, Patrick Torta, and Thomas Hartig,
“A 3-mW
uits Conferences, Page(s):527 – 530,Oct.
innis, Hans A. Hegt, and Arthur H. M.
IEEE J. Solid-State Circuits VOL.
37, NO.12, DECEMBER 2002
Ortmanns, M.; Gerfers, ta-Sigma A/D Converter
Implementation”
Advanced Signal Processing, Circuits, and System Design Techniques for Communications, Page(3):169-216, May 2006
[10] J. Arias and etc, “A 32-mW 320-MHz Continuous-Time Complex Delta-Sigm ADC for Multi-Mode Wireless-LAN Receivers,” IEEE J. Solid-State Circuits Vol. 41, No. 2, pp. 339-351, Feb. 2006.
[11] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, B. Romani, A.
Melodia, and V. Melini, "A 14b 20mW 640MHz CMOS CT ΣΔ ADC wi 20MHz Signal Bandwidth and 12b ENOB," in Proc. IEEE Int. Solid-State
Circuits Conf, 2006, pp. 62-63.
[12] M.Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion Springer, Berlin, Heidelberg, New York, 2006
[13] Lukas Dörrer, Fran
74-dB SNR 2-MHz Continuous-Time Delta-Sigma ADC With a Tracking ADC Quantizer in 0.13-μm CMOS” IEEE J. Solid-State Circuits VOL. 40, NO. 12, DECEMBER 2005
[14] Paton, S.; Poscher, T.; Di Giandomenico, A.; Kolhaupt, K.; Hernandez,
L.;Wiesbauer, A.; Clara, M.; Frutos, R.; “Linearity Enhancement Techniques in Low OSR, High Clock Rate Multi-bit Continuous-Time Sigma-Delta
Modulators” Custom Integrated Circ 2004
[15] Robert H. M. van Veldhoven, Brian J. M
van Roermund, “A 3.3-mW ΣΔ Modulator for UMTS in 0.18-μm CMOS With 70-dB Dynamic Range in 2-MHz Bandwidth”
[16] L. Risbo, ΣΔ Modulators - Stability Analysis and Optimization Technical University of Denmark, 1994.
[17] Tai-Haur Kuo; Kuan-Dar Chen; Jhy-Rong Chen; “
, Ph.D. thesis,
sign
Circuits and
m-33(No. 3):189.199, March 1985.
EE Transactions on Circuits and Systems -I, vol.
AB. Oregon State University,
Automatic coefficients de for high-order sigma-delta modulators” IEEE Transactions onSystems -I, Volume 46, Issue 1, Jan. 1999 Page(s):6 – 15
[18] J.C. Candy. .A Use of Double Integration in Sigma Delta Modulation IEEE
Transactions on Communication, vol. co
[19] O. Shoaei. .Continuous-Time Delta-Sigma A/D Converters for High Speed
Applications
PhD thesis, Carleton University, Ottawa, Canada, 1995.[20] R. Schreier and B. Zhang. .Delta-Sigma Modulators Employing Continuous-Time Circuitry..
IE
43(No. 4):324.332, April 1996.
[21] R. Schreier. The Delta-Sigma toolbox for MATL
http://www.mathworks.com, November 1999.
[22] L. Doerrer, A. Di Giandomenico, and A. Wiesbauer, "A 10-Bit, 4mW Continuous-Time Sigma-Delta ADC for UMTS in a 0.12um CMOS process Proc.
European Solid-State Circuits Con
," in
f, 2003, pp. 245-248.
age(s):I
-eim and R. Schafer, Discrete-Time Signal Processing, Prentice-Hall,
and Systems Volume 1, 25-28 July 2004
[23] Aboushady, H.; Louerat, M.-M. “Loop delay compensation in bandpass continuous-time ΣΔ modulators without additional feedback coefficients”International Symposium on Circuits and Systems, volume 1, 23-26 P
1124-7 Vol.1 May 2004[24] A. Oppenh 1989
[25] Beilleau, N.; Aboushady, H.; Louerat, M.M.;” Filtering adjacent channel blockers using signal-transfer-function of continuous-time ΣΔ modulators”
Midwest Symposium on Circuits
Page(s):I - 329-32 vol.1
[26] S. Yan and E. Sanchez-Sinencio, “A Continuous-Time ΣΔ with 88-dB Dynamic
uous-Time ΣΔ
ime
E, pages
Modulator,”IEEE J. Solid-State Circuits, Vol.
f Continuous Time Sigma Delta
ymp. Circuits
”
uits and System-I, Vol. 51, No.6, pp. 1088-1099, June
s, E. J. van der Zwan, and J. H. Huijsing, “Design for Optimum
roc.
e Range and 1.1-MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, Vol. 39, No. 1, Jan. 2004
[27] L.J. Breems, R. Rutten and G. Wetzker, “A Cascaded Contin
Modulator With 67-dB Dynamic Range in 10-MHz Bandwidth,” IEEE J.
Solid-State Circuits, Vol. 39, No. 12, pp. 2152-2160, Dec. 2004.
[28] F. Gerfers. A Design Strategy for Low-Voltage “Low-Power Continuous-T ΣΔ A/D Converters” In Design, Automation and Test Conference, DAT 361-368, 2001.
[29] F. Gerfers, M. Ortmanns, and Y. Manoli, “A 1.5V, 12-Bit Power Efficient Continuous Time Third-Order ΣΔ
38, No. 8, pp. 1343-1352, Aug. 2003.
[30] N. Wongkomet and B. E. Boser, “An Analysis o
Modulators,”
Electrical Engineering Conference No.21,1998
[31] M. Ortmanns, F. Gerfers, and Y. Manoli, “Influence of finite integrator gain bandwidth on CT sigma delta modulators,” in Proc. IEEE Int. S
Systems, vol. 1, May 2003, pp. 925–928.
[32] M. Ortmanns, F. Gerfers and Y. Manoli, “Compensation of Finite
Gain-Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators,
IEEE Transaction on Circ
2004.
[33] L. J. Breem
Performance to Power Ration of a Continuous Time ΣΔ Modulator,” in P
European Solid-State Circuits Conf., 1999, pp 318-321.
[34] J.A. Cherry and W.M. Snelgrove, “ Excess Loop Delay in Continuous-Tim
Delta-Sigma Modulators,”
IEEE Transactions on Circuit and System I, Vol.
eedback,” in Proc. IEEE Int. Conf. On Electronics, Circuits
lta
lid-State
ity,” IEEE TRANSACTIONS ON CIRCUITS AND
L. 49,
itz “A Transistor-based Clock Jitter
DAC,” IEEE Int.
and Systems, pp. 957-960, May2003.
Modelling and
B. Perez-Verdu, and A. Rodriguez-Vazquez, Top-Down Design of
on Circuit and System
46, No.4, pp. 376-389, April 1999.[35] O. Oliaei, “ Jitter Effects in Continuous Time ΣΔ Modulators with delayed Return-To-Zero F
and Syst., 1998, p. 351354.
[36] M. Ortmanns, F. Gerfers, and Y. Manoli, “A Continuous-Time Sigma –De Modulator with reduced Jitter Sensitivity,” in Proc. European So
Circuits Conf. 2002, pp. 287-290
[37] Susan Luschas, and Hae-Seung Lee,” High-Speed ΣΔ Modulators With Reduced Timing Jitter Sensitiv
SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VO
NO. 11, NOVEMBER 2002[38] F. Gerfers, M. Ortmanns, Philipp Schm
Insensitive DAC Architecture, IEEE ISCAS, pp. 21-24, May 2006.
[39] B. M. Putter, " ΣΔ ADC with finite impulse response feedback
Solid-State Circuits Conf. pp.76-77, Feb. 2004.
[40] O. Oliaei, “Continuous-time sigma-delta modulator incorporating semi-digital FIR filters, “IEEE Int. Symp. On Circuits
[41] L. Hernandez, A. Wiesbauer, S. Paton and A. Di Giandomenico,”
Optimization of Low Pass Continuous-Time Sigma-Delta Modulators for Clock Jitter noise Reduction,”
IEEE ISCAS, Vol. 1, pp. I- 1072-5, May 2004.
[42] F. Medeiro,
High Performance Sigma-Delta Modulators, Kluwer Academic Pub, 1999.
[43] J. A. Cherry, W. M. Snelgrove, “Clock jitter and quantizer metastability in continuous-time delta–sigma modulators,”
IEEE Trans.
II, vol. 46, pp. 661-676, June 1999.
[44] E.J. van der Zwan. “A 2.3mW CMOS ΣΔ Modulator for Audio Applications
ISSCC Digest of Technical Papers, p
” ages 220-221, February 1997.
e ΣΔ
9 K. Sweetland. “A 113-dB SNR Oversamplingte
low-pass passive sigma-delta modulator ,
CMOS continuous-time delta-sigma modulator
PA;
TS AND SYSTEMS—II:
ous
AC for a GSM-EDGE/CDMA2000/UMTS [45] H. Aboushady, J.R. Westra, and E.C. Dijkmans. “A 120 dB Dynamic Rang
DAC for Super Audio Compact Disc” Philips Research Report, December 199
[46] R. Adams, K.Q. Nguyen, andDAC with Segmented Noise-Shaped Scrambling”.IEEE Journal of Solid-Sta
Circuits,vol. 33(No. 12):1871.1878,
December 1998[47] F. Chen and B. Leung, "A 0.25 mW
with build-in mixer for a 10-MHz IF input," IEEE Journal of Solid-State Circuits vol. 32, no. 6, Jun. 1997.
[48] Song, T. Yan, S. Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA;“ A low power 1.1 MHz
with active-passive loop filters” IEEE ISCAS, pp.21-24, May 2006.
[49]Shoaei, O. Snelgrove, W.M. Bell Labs, Lucent Technol., Allentown,
“Design and implementation of a tunable 40 MHz-70 MHz Gm-C bandpass ΣΔ modulator” IEEE TRANSACTIONS ON CIRCUI
ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 7, JULY 1997.
[50] EJ, and DTJKMANS, EC: “A 0.2 mW CMOS modulator for speech coding with 80dB dynamic range” IEEE Journal of Solid-State Circuits, vol. 32, no. 6, Jun.
1997.
[51]Sansen, W.M.C.; Schoofs, R.; Steyaert, M.S.J.;” A Design-Optimized Continu Time Delta–Sigma ADC for WLAN Applications” IEEE Transactions on
Circuits and Systems -I, Volume 54, Jan. 2006 Page(s):209 – 217
[52] Robert H. M. van Veldhoven “A Triple-Mode Continuous-Time ΣΔ Modulator WithSwitched-Capacitor Feedback D
Receiver”
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12,
DECEMBER 2003[53] Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli ,“A 1 V, 12-Bit Wideband Continuous-Time Modulator ΣΔ for UMTS Applications” in Proc. IEEE
ISCAS,2003,pp. 921-924
[54] Toshiaki Nagai, Hiroyuki Satou, Hiroshi Yamazaki, Yuu Watanabe Fujitsu, Kawasaki, Japan,“A 1.2V 3.5mW ΣΔ Modulator with a Passive Current
erg, CMOS Analog Circuit Design. New York: Oxford Univ. Press, 2002.
with Summing Network and a Variable Gain Function” in Proc. IEEE
ISSCC ,2005,pp. 494-495.
[55] P. E. Allen and D. R. Holb
[56] G. M. Yin, F.Op’t Eynde, and W.Sansen “A High-Speed CMOS Comparator 8-b Resolut