CHAPTER 4 BUILT-IN-SELF-TEST CIRCUIT
4.1.2 CMFB
The CMFB we used here is implemented in SC circuits. Like Figure 4.4 shows,
capacitors labeled Cc generate the average output voltages, which are used to create control voltage (Vctrl) for current source of the opamp. The DC voltage across Cc is determined by capacitors Cs, which are switched between bias voltages and in parallel with Cc. The SC CMFB acts like a SC low-pass filter with DC input signal. Cs must be between 1/4 and 1/10 the sizes of Cc. Capacitor values are not critical to circuit perform, but with too small sizes will cause common-mode offset due to charge injection of the MOS switches. All switches are implemented by NMOS except those connected to the outputs (OUT and OUTb), which are realized by CMOS.
Chapter 4 Built-in-self-test Circuit
Cs Cc Cc
Vbias Vbias
Cs
OUT OUTb
Vctrl
φ1 φ2
φ1 φ2
φ1
φ2
φ1
φ2
Vcm Vcm
Figure 4.4 CMFB circuit
4.1.3 Simulation Results of TWG
Figure 4.5 is the simulation results of TWG. There are three signal lines in this figure:
two of the signal lines are differential triangular-waves and the other one is Vctrl. The differential triangular-waves oscillate between 1.15 V and 0.65 V, and the common-mode voltage is 0.9 V. Vctrl is the ctrl signal of CMFB circuit feedback to the opamp current source.
We find that Vctrl changes during a triangular-wave period and it affects the common-mode voltage of the opamp.
Figure 4.5 TWG simulation result
Figure 4.6 shows INL and DNL of the triangular-wave. We first subtract the differential triangular-waves to each other to obtain the single-ended signal wave. Then, sample voltage values of each test clock period. There are 1200 periods during a triangular-wave period in total. Then, compare the sampling data to the ideal values. Finally, we obtain DNL and INL of the pre-layout simulation result. Figure 4.7 shows DNL and INL of post-layout simulation result with the same method.
Vctrl
Chapter 4 Built-in-self-test Circuit
Figure 4.6 DNL and INL of TWG (pre-layout simulation)
Figure 4.7 DNL and INL of TWG (post-layout simulation)
From above two figures we see that DNLs of both the triangular-waves are close to perfect. The maximum DNL is only 0.25 mV. On the other hand, INL of the triangular-wave is the critical accuracy limitation. We can see the maximum INL of pre-layout simulation and post-layout simulation is 3.7 mV, which is equal to 7 bits resolution. The main factor of the INL errors is the Vctrl variation during a triangular-wave period. This term introduces
DNL INL
DNL INL
4.2 Output-response-analyzer
4.2.1 Dual-comparator
In this thesis, ORA includes a dual-comparator and a differential-to-single-ended circuit.
Dual-comparator is implemented due to one N-type and one P-type one-stage amplifier, shown in Figure 4.8. N-type amplifier takes high reference voltage (Vr+) as input and the P-type one takes low reference voltage (Vr-) as input. The output response frequency of SC filter would be very low, so the offset error of the dual-comparator is ignorable.
Figure 4.8 Dual-Comparator
Next, we describe the differential-to-single-ended circuit [13]. It is realized by SC circuit,
Vi Vr+ Vr- Vi
Vo
Vo
N-type amplifier P-type amplifier
Chapter 4 Built-in-self-test Circuit
the amplifier is reset. Except that, it is also insensitive to low opamp gain.
4.2.2 Differential-to-single-ended Circuit
First, Figure 4.9 is a capacitive-reset gain circuit. Capacitor Cd is an optional deglitching capacitor. It is used to provide continuous-time feedback during the nonoverlapping clock times when all switches are turned off. The gain circuit can be either inverting or
non-inverting depending on the clock phases of the input stage. To see how this circuit operates, consider during the reset phase ofφ , as shown in Figure 4.10(a). C3 is charged to 2 the output voltage during the previousφ phase, so output voltage does not reset to zero 1 during reset phase, which is different from the traditional resettable gain circuit [14]. At this phase C1 and C2 are charged to the input offset voltage of the opamp. The next valid output phase ofφ is shown in Figure 4.10(b). In this figure we see the output voltage is independent 1 of the offset voltage.
Figure 4.9 Capacitive-reset gain circuit +
-a
φ2 a
φ
1φ1
φ2
φ1
φ2
b
φ1
Vi
C1
C2 C3
Cd
Vo
b
φ1
+
Figure 4.10 Capacitive-reset gain circuit (a) reset phase (b) valid output phase
Figure 4.11 shows complete structure of the differential-to-single-ended circuit. In this circuit, C1 is equal to C2 in order to make the closed-loop gain unity. Besides, switches connected to analog ground and virtual ground are realized by NMOS, others are realized by CMOS for large operating swing. Assuming the opamp has finite open-loop gain A, its transfer function in the z-domain is found to be
1
Chapter 4 Built-in-self-test Circuit
For low frequency z is approximately equal to unity and (4-1) can be rewritten as
)
From (4-4) we can find the gain error is proportional to A-2, which is much more insensitive to open-loop gain error than the traditional gain circuit.
+
Figure 4.11 Differential-to-single-ended circuit
4.2.3 Simulation Results of the Differential-to-single-ended Circuit
Figure 4.12 is the simulation results when input signal is a pair of differential sine-waves at 1 MHz. The maximum glitch of the output is 100 mV. Figure 4.13(a) and (b) are the DNL and INL analysis results with input signals are differential triangular-waves at 40 KHz. Upper figures of 4.13(a) and (b) are the sampled data of output voltages and lower figures of 4.13(a) and (b) are the DNL and INL results. From these figures we find that the errors increase rapidly when output voltage is close to analog ground because output voltage moves up and down.
Chapter 4 Built-in-self-test Circuit
Figure 4.12 Simulation results of the differential-to-single-ended circuit
(a) (a)
Differential input Single-ended output
(b) (b)
Figure 4.13 (a) DNL and (b) INL results of the differential-to-single-ended circuit
4.3 Top Architecture and Simulation Result
Figure 4.14 is top architecture of the total design. We see that two cascading biquad filters introduced in Chapter 3 are taken as the core circuits. Except that, TWG applies differential test input waveforms for the core circuit, which are connected to aBUS1 and aBUS1b. Differential-to-single-ended circuit and dual-comparator receive the test output responses from one of the biquad filters, which are connected to aBUS2 and aBUS2b.
Switches (S0 ~ S3) determine the circuit operating in the normal mode or the test mode, and
Chapter 4 Built-in-self-test Circuit
these switches are controlled by the test1 and the test2 signals. For example, if {test1, test2} is {0, 0}, the circuit operates in the normal mode. In this case, S0 will turn on and others turn off, differential input signals will from IN and INb transmit to OUT and OUTb through the
4th-order low-pass filter. If {test1, test2} is equal to {1, 0} or {0, 1}, the circuit operates in the test mode. Biquad1 will be taken as core circuit and switches S1 turn on for the case of {1, 0}.
Similarly, Biquad2 will be taken as core circuit and switches S2 turn on for the case of {0, 1}.
The differential test output responses (aBUS2, aBUS2b) will be transferred into single-ended type (aBUS2s) and be analyzed by the dual-comparator.
IN
INb
CLK
Vref+
Vref-OUT
OUTb
TDO1
TDO2 aBUS1b aBUS2b
Biquad1 Biquad2
Clk Driver
TWG
S0 S1 S1 S0 S2 S2 S0
S0 S1 S1 S0 S2 S2 S0
aBUS2 aBUS1
Test1
Differential-to-Single-ended
Test2 Logic
dual-comparator aBUS2s
Figure 4.14 Top architecture
We have already described the concept of the test approach and the equation for computing probabilities in Chapter 2. Now, we compare the derived probabilities to the simulation results and discuss the reason of the difference between these two terms.
First, we discuss the case of gain error. We totally compare 9 cases here. Figure 4.15(a) shows the derived probabilities of each case and Figure 4.15(b) shows the BIST circuit simulation results. The unit of X-axis is percentage. Theoretically, S1 should always be equal to S3. However, from Figure 4.15(b), we see the case of -10%, -15% and -20%, the difference between S1 and S3 becomes larger gradually. This is because the triangular-waves itself have offset voltages.
* P1 o P2 ^ P3
(a) (b)
* S1 o S2 ^ S3
Figure 4.15
Figure 4.16 (a), (b), (c) show the comparison between P1-S1, P2-S2 and P3-S3 of gain errors. We find the simulation results are very close to the probabilities except the cases of -10%, -15% and -20%. This is because the input test waveform is not accurate enough in
Chapter 4 Built-in-self-test Circuit
(a) (b) (c)
* Probability o Simulation
Figure 4.16
Next, we will discuss the case of offset error. Figure 4.17(a) and (b) show derived probabilities (P1, P2, P3) and simulation results (S1, S2, S3) of offset errors. The unit of X-axis is voltage. Due to Figure 4.17(b) we find that simulation results have errors in the cases of 0.1, 0.15 and 0.2. This is because the core circuit output responses generate amplitude errors in these cases and this reason affects the test results.
* P1 o P2 ^ P3
(a) (b)
* S1 o S2 ^ S3
Figure 4.18 (a), (b), (c) show the comparison between P1-S1, P2-S2 and P3-S3 of offset errors. We see the simulation results are very close to the probabilities except the cases of 0.1, 0.15 and 0.2. This is because the output responses generate the amplitude errors.
Figure 4.18
4.4 Layout Consideration and Implementation
In this section, we will describe layout considerations of some key-points, such as power-lines, capacitors and layout placement of the top circuit. The total area of the layout is 1.65(mm) * 1.3(mm) and total power is 72 mW.
(a) (b) (c)
* Probability o Simulation
Chapter 4 Built-in-self-test Circuit
4.4.1 Power Lines
Assume we use the approach shown in Figure 4.19(a) for the power lines connecting. It will cause a voltage drop exists inside the chip, which is called power-supply coupling effect.
To avoid this problem, we apply two independent pair of pins for the connection of analog power lines and digital power lines. Like Figure 4.19(b) shows.
Digital Digital Pin Digital Pad
Analog Pin Analog Pad
L L1
L2
(b)
Figure 4.19 Layout consideration of power lines
4.4.2 Capacitors
For high accuracy of the capacitances, we use MIM structure to realize the capacitors of SC circuits because another approach, MOS capacitors are sensitive to the bias voltage and temperature. Figure 4.20 shows the structure of the MIM capacitor.
Figure 4.20 MIM capacitor structure M6
CTM5 M5 Via56
4.4.3 Top Layout Placement Considerations
Placement of the top layout is shown in Figure 4.21. This approach is suit for all SC circuits. Switches and digital circuits cause large impulse current during operating, which will introduce large substrate coupling noise. Substrate coupling noise affects analog circuits seriously because all circuits are placed on the same substrate. We have to use some layout skills to reduce this effect.
First, we place switches and digital circuits far away from analog circuits. As shown in Figure 4.21, we place the capacitor array in the center of the whole chip to divide analog circuits apart from digital circuits and switches. Except that, we use the approach of N-well shielding. We place the capacitor array in N-well and apply an additional power-supply VDD for the N-well to isolate the noise from substrate coupling. Second, we place analog power lines surrounding all of the analog blocks, which is called guard ring. This approach can protect circuits in the guard ring from the outside noise affecting. The third approach is dividing source of all digital transistors from the substrate in order to reduce substrate coupling. As shown in this figure, we apply an independent power line GNDd, which connects sources of all digital transistor together but not connect to VSSd (substrate) inside the chip.
Chapter 4 Built-in-self-test Circuit
VDDa
VSSa Analog Circuit
N_well
VDD Capacitor Array
GNDa Routing Lines
VDDd Switches
VSSd Digital Circuit
GNDd
Figure 4.21 Placement of the top layout
Total layout is shown in Figure 4.22. The technology we use here is TSMC CMOS 0.18um 1P6M. The area is 1.65(mm)*1.3(mm) and power consumption is 72 mW. We also show the area and power proportion of BIST which occupies in the total circuit in Figure 4.23.
analog
bypass capacitor
capacitor array
switches
& digital
Figure 4.22 Layout of the high bandwidth, 4th-order, SC low-pass filter and the BIST circuit
BIST
(a) Area
21%
(b) Power
32%
Figure 4.23 Area and power proportion of BIST
Chapter 5 Conclusion and Future Work
Chapter 5
Conclusion and Future Work
5.1 Conclusion
How to achieve on-chip testing of analog circuits with lower cost is the critical issue for today’s mixed-signal testing. In this thesis, we design a fully-differential, 140 MHz
sampling frequency, 10 MHz corner frequency, 4th-order low-pass SC filter. Except that, we take the SC filter as the core circuit and design the BIST circuit for the SC filter. The test approach we adopted is taking triangular-wave as input waveform and comparing the
probability of the self-test results to the derived results to estimate the gain error and the offset error. In our design, there is a test-waveform-generator, which generates a 29.2 KHz, 7 bits resolution, differential triangular-waves, and an output-response-analyzer, which includes a differential-to-single-ended circuit and a dual-comparator.
5.2 Future Work
There are some key-points should be improved in this thesis:
(1) Bandwidth of opamp: we implement a fully-differential opamp with unity-gain frequency at 770 MHz, if we achieve higher bandwidth, we can make the system operating in higher sampling frequency.
(2) Resolution of the triangular-wave: we achieve 7 bits resolution in this thesis, and we find the main accuracy limitation is because of the CMFB. It introduces
common-mode voltage error during a period.
(3) DNL and INL error of differential-to-single-ended circuit: The DNL and INL error increase rapidly when output voltage close to analog ground. How to solve this problem is an important point of future works.
(4) Controllable-frequency TWG: We realize a TWG with a fixed-frequency test waveform. However, we can add some digital circuits to achieve
controllable-frequency capability.
Chapter 5 Conclusion and Future Work
Reference
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[3] Khaled, S., Kaminska, B., Courtois, B., Lubaszewski, M., “Frequency-based BIST for analog circuit testing”, VLSI Test Symposium, 1995. Proceedings., 13th IEEE, 30 April-3 May 1995, Pages:54 - 59
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