6.1 Conclusions
Based on the exact solution of 3-D Poisson equation, a new analytical model comprising channel potential, threshold voltage, subthreshold swing and subthreshold current for dual-material gate SOI MESFETs and MOSFETs have been developed. It is found that the thin silicon film is preferred to alleviate short channel effects and has a tendency to induce small threshold voltage roll-off and subthreshold swing degradation.
6.2 Future Works
As for the future work, the following researching tasks are suggested:
1. The present study can be well expended to quantum mechanic effect by Schrodinger equation.
2. The present study can also be applied to the SOI MOSFET with localized interface trapped charges or SOI MESFET with localized bulk trapped charges.
3. The present study can also be applied to the high-frequency communication circuit analysis or SPICE simulation.
References
1. J. D. Marshall, and J. D. Meindl, "A sub- and near-threshold current model for silicon MESFETs," IEEE Trans. Electron Devices, vol. 35, no. 3, pp. 388-390, March, 1988.
2. Q. Chen, M. Willander, C. H. Thaki, and E. R. A. Evans, "Fabrication and performances of delta-dopped Si n-MESFET grown by MBE," Electron Lett., vol.
29, no. 8, pp. 671-673, April, 1993.
3. G. V. Ram, and M. I. Elmasry, "On the scalling of Si-MESFET’s," IEEE Trans.
Electron Devices, vol. 1, no. 12, pp. 259-262, Dec., 1980.
4. P. A. Tove, K. Bohlin, F. Masszi, H. Norde, J. Nylander, J. Tiren, and U.
Magnusson, "Complementary Si MESFET concept using silicon on sapphire technology," IEEE Trans. Electron Devices Lett., vol. 9, no. 1, pp. 47-49, Jan., 1988.
5. K. P. Macwilim, and J. D. Plummer, "Device physics and technology of complementary silicon MESFET’s for VLSI applications," IEEE Trans. Electron Devices, vol. 38, no. 12, pp. 2619-2631, Dec., 1991.
6. Y. Tosaka, K. Suzuki, and T. Sugii, "Scaling-parameter-dependent model for subthreshold swing in double-gate SOI MOSFETs," IEEE Trans. Electron Devices Lett., vol. 15, no. 11 pp. 466-468, Nov., 1994.
7. R. V. Tuyl, and C. Liechti, "High-speed integrated logic with GaAs MESFETs,"
Solid-State and Integrated Circuit Technology, pp. 114-115, Jun., 1974.
8. X. Yang, X. Zheng, and J. Hao, "Direct coupled FET logic (DCFL) circuit for GaAs LSIC application," Microwave and Millimeter Wave Technology Proceeding, vol. 12, no. 5, pp. 913-916, 1998.
9. T. K. Chiang, "The new analytical subthreshold behavior model for dual material gate (DMG) SOI MESFET," Solid-State and Integrated Circuit Technology, pp.
288-189, Oct., 2008.
10. 吳朝允, 2009 "雙材質閘極具氧化層基體絕緣結構之矽金半場效電晶體與砷 化鎵鋁/砷化鎵異質結構場效電晶體之次臨界行為研究," 南台科技大學電子 工程研究所碩士論文。
11. T. Khan, D. Vasileska, and T. J. Thornton, "Subthreshold electron mobility in SOI MOSFETs and MESFETs," IEEE Trans. Electron Devices, vol. 52, no. 7, pp.
1622-1626, July, 2005.
12. W. Long, H. Ou, J. M. Kuo, and K. K. Chin, "Dual material gate (DMG) field effect transistor," IEEE Trans. Electron Devices, vol. 46, no. 5, pp. 865-870, May, 1999.
13. K. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399-402, Feb., 1989.
14. P. C. Yen, and J. G. Fossum, "Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology," IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1605-1613, Sep., 1995.
15. M. Saxena, S. Haldar, M. Gupta, and R. S. Gupta, "Physcis-Based analytical modeling of potential and electrical field distribution in Dual Material Gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1928-1938, Nov., 2002.
16. M. J. Kumar, and A. Chaudhry, "Two-Dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs," IEEE Trans.
Electron Devices, vol. 51, no. 4, pp. 569-574, April, 2004.
17. DEVICE, Three-dimensional device simulation program. ISE-TCAD, 2003.
18. P. Pandey, B. B. Pal, and S. Jit, "A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFETs," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 246-256, Feb., 2004.
19. D. Z. Pilja, "An analytical 3-D model for small dimensions MOSFETs' threshold voltage," PROC. 22nd International Conference on Microelectronics (MIEL2000), vol. 1, NIS, SERBIA, May, 2000.
20. N. B. Balamurugen, M. Balasubadra, and K. Suguna, "A new analytic description of short-channel effects in fully depleted single gate SOI MESFETs for low power VLSI application," IEEE-ICSCN 2007, pp. 382-387, Feb., 2007.
21. S. P. Kumar, A. Agrawal, R. Chaujar, S. Kabra, M. Gupta, and R. S. Gupta,
"3-Dimensional analytical modeling and simulation of fully depleted AlGaN/GaN modulation doped field effect transistor," Physics of Semiconductor Devices, pp. 373-376, Dec., 2007.
22. P. Hashemi, A. Fathi, and E. A. Kusha, "Two-Dimensional analytical modeling and simulation of the potential and threshotd voltage of a new fully depleted dual metal gate SOI MESFET," IEEE Transactions on Electron Devices, pp. 372-375, Dec., 2004.
23. J. G. Cao, "A simplified 2-D analytic model for the threshold-voltage of fully depleted short gate-length Si-SOI MESFETs," IEEE Transactions on Electron Devices, vol. 43, pp. 1314-1315, Aug., 1996.
24. B. Agrawal, and J. D. Meindl, "Three-dimensional analytical subthreshold models for bulk MOSFETs," IEEE Transactions on Electron Devices, vol. 42, no.
12, pp. 246-256,Dec., 1995.
25. T. K. Chiang, Y. H. Wang, and M. P. Houng, "Modeling of threshold voltage and subthreshold swing of short-channel SOI MESFETs," Solid-State Electronics, vol.43, no. 1, pp. 123-129, 1998.
26. S. Jit, P. Pandey, and B. B. Pal, "A new two-dimensional model for the drain-induced barrier lowering of fully depleted short-channel SOI-MESFET’s,"
Journal of Semiconductor Technology and Science, vol.3, no. 4 , pp. 217-222, Dec., 2003.
27. X. Zhou, and W. Long, "A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology," IEEE Trans. Electron Devices, vol. 45, no.
12, pp. 2546-2548, Dec., 1998.
28. S. Jit, S. Morarka, and S. Mishra, "A 2-D model for the potential distribution and threshold voltage of fully depleted short-channel ion-implanted silicon MESFETs," Journal of Semiconductor Technology and Science, vol. 5, pp.
173-181, March, 2005.
29. 楊鳴傑, 2010 "四閘極電晶體具氧化層基體絕緣結構之短通道行為研究," 國 立高雄大學電機工程研究所碩士論文。
30. T. Yuan, and X. Liang, "A 2-D analytical solution for SCEs in DG MOSFETs,"
IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1385-1391, Sep., 2004.
31. N. Lakhdar, F. Djeffal, M. A. Adbi, and D. Arar, "An analytical threshold voltage
model to study the scaling capability of deep submicron double-gate GaN-MESFETs," International Workshop on symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010.
32. E. Hamid, H. A. Guitart, and B. Iniguez, "Two-Dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1402-1408, June, 2007.
33. A. I. Khan, M. K. Ashraf, and A. Haque, "Influence of wave function penetration on short channel effects in nanoscale double gate MOSFETs," Electron Device and Solid-State Circuit, pp. 109-112, Dec., 2007.
34. H. Abd, J. R. Guitart, and V. Kilchytska, "A 3-D analytical physically Based model for the subthreshold swing in undoped trigate FinFETs," IEEE Trans.
Electron Devices, vol. 54, no. 9, pp. 2487-2496, Sept., 2007.
35. Q. Chen, B. Agrawal, and J. D. Meindl, "A comprehensive analytical subthreshold swing model for double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 1086-1090, June, 2002.
36. J. D. Marshall, and J. D. Meindl, "An analytical two-dimensional model for silicon MESFET’s," IEEE Trans. Electron Devices, vol. 35, no. 3, pp. 373-383, March, 1988.
37. Y. Tosaka, K. Suzuki, and T. Sugii, "Scalling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 15, no. 11, pp. 466-468, 2004.
38. S. Jit, P. K. Pandey, and P. K. Tiwari, "Modeling of the subthreshold current and subthreshold swing of fully depleted short-channel Si-SOI-MESFTEs,"
Solid-State Electronics, pp. 57-62, 2009.
39. M. S. Islam, M. Hasan, and M. R. Islam, "An improved nonlinear DC I-V characteristics model for nanometer range GaAs MESFETs," TENCON 2009-2009 IEEE Region 10 Conference, pp. 1-5, 2009.
40. S. Jit, P. K. Pandey, and P. K. Tiwari, "Modeling of the subthreshold current and subthreshold swing of fully depleted short-channel Si-SOI-MESFETs,"
Solid-State Electronics, vol. 53, no. 1, pp. 57-62, Jan., 2009.
41. Y. Taur, X. Liang, W. Wang, and H. Lu, "A continuous analytic drain-current
42. H. S. Wong, D. J. Frank, and P. M. Solomon, "Device design consideration for double-gate, ground-gated ultran-thin SOI MOSFETs at the 25nm channel length generation," IEDM Tech. Dig., pp. 407-410, 1998.
43. M. Saxena, S. Haldar, M. Gupta, and R. S. Gupta, "Physics-Based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1928-1938, Nov., 2002.
44. K. Suzuki, "Analytical threshold voltage model for short channel double gate MOSFET’s," IEEE Trans. Electron Devices, vol. 43, no. 7, pp. 1166-1168, July, 1996.
45. K. Suzuki, Y. Tosaka, and T. Sugii, "Analytical model for n+-p+ double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 42, no. 11, Nov., 1995.
46. S. Odanaka, "Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures," IEEE TACD, vol. 23, no.
6, pp. 837-842, June, 2004.
47. D. Munteanu, J. L. Autran, P. Paillet, J. Baggio, O. Faynot, C. Jahan, and L. Tosti,
"Investigation of quantum effects in ultra-thin body single- and double-gate devices submitted to heavy ion irradiation," IEEE Trans. Nuclear Science, vol. 53, no. 6, pp. 3363-3371, Dec., 2006.
48. D. Munteanu, J. L. Autran, P. Paillet, J. Baggio, and K. Castellan, "3D quantum numerical simulation of single-event transient in multiple-gate nanowire MOSFETs," IEEE Trans. Nuclear Science, vol. 54, no. 4, pp. 994-1001, Aug., 2007.
49. Y. S. Wu, and P. Su, "Analytical quantum-confinement model for short-channel gate-all-around MOSFETs under subthreshold region," IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2720-2725, Nov., 2009.
50. S. A. Hareland, S. Jallepalli, G. Chindalore, W. K. Shin, A. F. Tasch, and C. M.
Maziur, "A simple model for quantum mechanical effects in hole inversion layers in silicon PMOS device," Solid-State Electron., vol. 44, no. 7, pp. 1172-1173, Mar., 1997.
51. J. Knoch, M. Zhang, and S. Mantl, "On the performance of single-gated ultrathin-body SOI Schottky-Barrier MOSFETs," IEEE Trans. Electron Devices,