三維雙材質具氧化層基體絕緣結構之矽金半場效電晶體和金氧半場效電晶體之次臨界行為研究

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(1)國立高雄大學電機工程學系電機工程研究所碩士論文. 三維雙材質具氧化層基體絕緣結構之矽金半場效電晶體和金氧半場效電晶體之次臨界行為研究 The Investigation on Subthreshold Behavior Model for the Three Dimensional Dual-Material Gate SOI MESFETs and MOSFETs. 研究生：賴俊帆撰指導教授：江德光博士. 中華民國一百年五月.

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(3) 三維雙材質具氧化層基體絕緣結構之矽金半場效電晶體和金氧半場效電晶體之次臨界行為研究指導教授：江德光博士國立高雄大學電機工程系電機工程研究所學生：賴俊帆國立高雄大學電機工程系電機工程研究所摘要. 近年來雙材質閘極(Dual-material gate)的金半場效電晶體(MESFET)和金氧半場效電晶體(MOSFET)已經引起了許多的學者廣泛的注意和研究，和一般傳統的單材質閘極結構(Single-material gate)的 MESFET 和 MOSFET 相比較，雙材質閘極電晶體在尺度微縮上有較大的空間和優勢，例如，雙材質在接面處提供了一個步階電位，和一個高電場，這可以提供電子做中段加速，且在接近汲極端處的電場會明顯的低於單閘極電晶體，這現象可以降低了熱載子效應，另外也具備了較理想的次臨界斜率和較低的閘極漏電流，更符合目前電子電路設計傾向奈米級尺寸的需求。本論文乃基於帕森方程式之全三維解，成功地推導出三維雙材質結構之金半場效電晶體(MESFET)和金氧半場效電晶體(MOSFET)模型，此模型不僅準確顯示出電位分佈 (potential distribution) 、電場分佈 (electric field distribution) 、次臨界電流 (subthreshold current)、和次臨界斜率(subthreshold slope) 、和短通道臨界電壓縮減 (threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering) 等效應，而且此模型之演算結果與模擬數據相當接近，足以提供基本元件設計之導向，並進而被應用於積體電路之模擬。. 關鍵字：雙材質金半場效電晶體、雙材質金氧半場效電晶體、短通道行為、帕森方程式、短通道臨界電壓縮減. i.

(4) The Investigation on Subthreshold Behavior Model for the Three Dimensional Dual-Material Gate SOI MESFETs and MOSFETs Advisor: Dr. TE-KUANG CHIANG Department of Electrical Engineering, Institute of Electrical Engineering, National University of Kaohsiung Student: CHUN-FAN LAI Department of Electrical Engineering, Institute of Electrical Engineering, National University of Kaohsiung ABSTRACT In recent years, dual-material gate SOI MESFETs and MOSFETs have already caused extensive attention by some researches due to the dual-material gate has larger space and advantage on length scaling when in comparison to conventional single-material gate devices. Dual-material gate (DMG) MESFETs and DMG MOSFETs effectively induce the step potential as well as peak electric fields within the channel improve the carrier transit speed. In comparison to Single-material gate (SMG) device, it is obviously observed that the DMG device has the lower electrical field near the drain side that it will decrease the hot carrier effect (HCE). In addition, because DMG SOI MESFETs and MOSFETs have better swing and lower gate leakage current than SMG device, they are good candidates to apply to the high-frequency communication circuits. In this thesis, based on the exact solution of the Poisson equation, we successfully develop an analytical short-channel subthreshold behavior model for SOI MESFETs and MOSFETs. These analytical results are useful in predictive compact modeling of SOI MESFETs and MOSFETs. The model explicitly shows the distribution of electric potential, the distribution of electric potential, subthreshold current, subthreshold slope, short channel threshold voltage roll-off, and drain-induced-barrier-lowing (DIBL) effect. The model is verified by the published numerical simulations with close agreement. This model not only gives the physical insights into the device physics but also offers the basic designing guidance of the DMG devices. Due to its computational efficiency, this model can be applied for SPICE simulation. Keywords: Dual-material gate MESFETs, Dual-material gate MOSFETs, Short channel effects, Poisson equation, Threshold voltage roll-off.. ii.

(5) Acknowledgements. I am grateful to many people with deep sincerity. This work will not be completed without their support and assistance. First I would like to express my most sincere gratitude to my advisor, Professor T. K. Chiang for his guidance in this work. I would also like to thank many of the past and present members of our research group for their spiritual support and useful discussion.. Finally, I am deeply grateful to my parents for their patience and concern. I could never accomplish the work without their love and advice during these years.. iii.

(6) Contents. 摘要. i. Abstract. ii. Acknowledgements. iii. Contents. iv. List of Figures. vi. Chapter 1 Introduction. 1. 1.1. MESFETs Devices Overview. 1. 1.2. MOSFETs Devices Overview. 7. Chapter 2 Three Dimensional Potential and Threshold Voltage Model for Dual-Material Gate SOI MESFETs. 13. 2.1. Model Derivation. 13. 2.2. 3-D Boundary Conditions Value Problem. 15. 2.3 1-D Solution. 18. 2.4 2-D Coefficients Solution. 20. 2.5. 23. 3-D Laplace Equation Solution. 2.6 3-D Generalized Potential Model. 28. 2.7. Minimum Channel Potential. 38. 2.8. Electric Field and Potential Contour. 41. 2.9. Threshold Voltage Roll-off Model. 45. 2.10. Threshold Voltage by Considering the Quantum Mechanics Effect. 53. 2.11. Conclusions. 57. iv.

(7) Chapter 3 Three Dimensional Subthreshold Current Model for Dual-Material Gate SOI MESFETs. 58. 3.1 Subthreshold Slope Model. 58. 3.2. Subthreshold Current Model. 64. 3.3. Conclusions. 70. Chapter 4 Three Dimensional Potential and Threshold Voltage Model for Dual-Material Gate SOI MOSFETs. 71. 4.1. Model Derivation. 71. 4.2. 3-D Boundary Conditions Value Problem. 73. 4.3. 1-D, 2-D, and 3-D Solution. 75. 4.4 3-D Generalized Potential Model. 82. 4.5. Minimum Channel Potential. 91. 4.6. Electric Field and Potential Contour. 93. 4.7. Threshold Voltage Roll-off Model. 97. 4.8. Threshold Voltage by Considering the Quantum Mechanics Effect. 103. 4.9. Conclusions. 109. Chapter 5 Three Dimensional Subthreshold Current Model for Dual-Material Gate SOI MOSFETs. 110. 5.1 Subthreshold Slope Model. 110. 5.2. Subthreshold Current Model. 113. 5.3. Conclusions. 117. Chapter 6 Conclusions and Future Works. 118. 6.1. Conclusions. 118. 6.2. Future Works. 118. References. 119. v.

(8) List of Figures Fig. 1.1 Schematics of DCFL (a) Inverter (b) 3-input NOR gate [8].………………………....2 Fig. 1.2 ISE simulation results of MESFET for the electron distributions................................4 Fig. 1.3 Variation of the electron concentration along the channel thickness for the MESFET at V ds =1.0V... .............................................................................................................................4 Fig. 1.4 ISE simulation results of SMG and DMG devices for the bottom potential................5 Fig. 1.5 ISE simulation results of SMG and DMG devices for the electric field. .....................5 Fig. 1.6 ISE simulation results of SMG device for the potential contours. Device parameters are t si =40 nm, t ox =300 nm, W=150 nm, and L=500 nm.............................................................6 Fig. 1.7 ISE simulation results of DMG device for the potential contours. Device parameters are t si =40 nm, t ox =300 nm, W=150 nm, and L 1 =L 2 =250 nm.....................................................6 Fig. 1.8 (a) Circuit diagram of a CMOS inverter. (b) Output voltage response applying a step function at the input [9]..............................................................................................................7 Fig. 1.9 ISE simulation results of MOSFET for the electron distributions. ............................10 Fig. 1.10 Variation of the electron concentration along the channel thickness for the MOSFET at V ds =1.0V.. ...........................................................................................................10 Fig. 1.11 ISE simulation results of SMG and DMG devices for the surface potential............11 Fig. 1.12 ISE simulation results of SMG and DMG devices for the electric field.. ................11 Fig. 1.13 ISE simulation results of SMG for the potential contours. Device parameters are t si =40 nm, t ox1 =5 nm, t ox2 =50 nm, W=80 nm, and L=300 nm.. ...............................................12 Fig. 1.14 ISE simulation results of DMG device for the potential contours. Device parameters are t si =40 nm, t ox1 =5 nm, t ox2 =50 nm, W=80 nm, and L 1 =L 2 =150 nm....................................12 Fig. 2.1 The 3-D structure for DMG SOI MESFETs...............................................................13 Fig. 2.2 The decay of Fourier series P n and R n coefficients versus the term number .............22 Fig. 2.3 The decay of Fourier series T mn coefficients versus the term number (the value of m used for simulation is from 1 to 10, the value of n used for simulation is from 1 to 10). .......27 Fig. 2.4 The 3-D potential distribution from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, y = t si and V ds = 1V. ............................................................29 Fig. 2.5 The 3-D potential distribution from model results for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, y = t si and V ds = 1V. .........................................................................................29 Fig. 2.6 The 3-D potential distribution from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 1 : 3, y = t si and V ds = 1V.............................................................30 vi.

(9) Fig. 2.7 The 3-D potential distribution from model results for DMG SOI MESFETs device L 1 : L 2 = 1 : 3, y = t si and V ds = 1V ........................................................................................30 Fig. 2.8 The 3-D potential distribution from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 3 : 1, y = t si and V ds = 1V.............................................................31 Fig. 2.9 The 3-D potential distribution from model results for DMG SOI MESFETs device L 1 : L 2 = 3 : 1, y = t si and V ds = 1V..........................................................................................31 Fig. 2.10 The 3-D potential distribution from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, x = W/2 and V ds = 1V. .........................................................32 Fig. 2.11 The 3-D potential distribution from model results for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, x = W/2 and V ds = 1V. ......................................................................................32 Fig. 2.12 The 3-D potential distribution from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 1 : 3, x = W/2 and V ds = 1V. .........................................................33 Fig. 2.13 The 3-D potential distribution from model results for DMG SOI MESFETs device L 1 : L 2 = 1 : 3, x = W/2 and V ds = 1V.. .....................................................................................33 Fig. 2.14 The 3-D potential distribution from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 3 : 1, x = W/2 and V ds = 1V. .........................................................34 Fig. 2.15 The 3-D potential distribution from model results for DMG SOI MESFETs device L 1 : L 2 = 3 : 1, x = W/2 and V ds = 1V.. .....................................................................................34 Fig. 2.16 The variation of the bottom potential with the normalized channel position for the different ratios of L 1 and L 2 .....................................................................................................36 Fig. 2.17 The variation of the bottom potential with the normalized channel position for the different silicon thicknesses .....................................................................................................36 Fig. 2.18 The variation of the bottom potential with the normalized channel position for the different drain biases................................................................................................................37 Fig. 2.19 The variation of the bottom potential with the normalized channel position for the different work functions...........................................................................................................37 Fig. 2.20 The dependence of minimum potential on the gate bias for the different the cannel lengths ......................................................................................................................................39 Fig. 2.21 The dependence of minimum potential on the gate bias for the different silicon thicknesses... ............................................................................................................................40 Fig. 2.22 The variation of the electric field with the normalized channel position for the different ratios of L 1 and L 2 .....................................................................................................42 Fig. 2.23 The 3-D electric field from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, y = t si and V ds = 1V.. .............................................................................43 vii.

(10) Fig. 2.24 The 3-D electric field from model result for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, y = t si and V ds = 1V..........................................................................................................43 Fig. 2.25 Constant electrostatic potential contours based on the analytical solution (solid curves) for DMG MESFETs, compared with ISE simulation results (dash curve). Here, V ds = 1V, L=500 nm, and L 1 : L 2 = 1 : 1. .......................................................................................44 Fig. 2.26 The dependence of threshold voltage roll-off on the channel length for the different ratios of L 1 and L 2 .....................................................................................................51 Fig. 2.27 The dependence of threshold voltage roll-off on the channel length for the different work functions of M 2 ................................................................................................51 Fig. 2.28 The dependence of threshold voltage roll-off on the channel length for the different silicon film thicknesses .............................................................................................52 Fig. 2.29 The dependence of threshold voltage roll-off on the channel length for the different silicon film widths.....................................................................................................52 Fig. 2.30 (a) 3-D electron density distribution of Y-Z plane for the middle of channel width in the classical case ..................................................................................................................54 Fig. 2.30 (b) 3-D electron density distribution of Y-Z plane for the middle of channel width in the quantum case..................................................................................................................54 Fig. 2.31 The quantum and classical electron density distribution in a vertical cut-line in the middle of the channel...............................................................................................................55 Fig. 2.32 Drain current simulated in classical and quantum case for the different silicon thicknesses. ..............................................................................................................................55 Fig. 2.33 The threshold voltage versus the channel length for the different silicon film thicknesses in classical and quantum case ...............................................................................56 Fig. 3.1 The subthreshold swing versus the channel length for the different ratios of L 1 and L 2 ..............................................................................................................................................62 Fig. 3.2 The subthreshold swing versus the channel length for the different silicon film thicknesses ...............................................................................................................................62 Fig. 3.3 The subthreshold swing versus the channel length for the different work functions. 63 Fig. 3.4 The minimum potential versus L 1 for the different ratios of L 1 and L 2 .. ...................65 Fig. 3.5 The minimum potential versus L 1 for the different silicon film widths .....................66 Fig. 3.6 The minimum potential versus L 1 for the different silicon film thicknesses .............66 Fig. 3.7 The subthreshold current versus the gate bias for the different ratios of L 1 and L 2 ..68 Fig. 3.8 The subthreshold current versus the gate bias for the different silicon widths ..........68 Fig. 3.9 The subthreshold current versus the gate bias for the different silicon thicknesses...69 viii.

(11) Fig. 3.10 The subthreshold current versus the gate bias for the different channel lengths......69 Fig. 4.1 The 3-D structure for DMG SOI MOSFETs.. ............................................................71 Fig. 4.2 The contour plot of the electrostatic scaling length versus insulator thickness and silicon thicknesses for SOI MOSFETs.. ..................................................................................78 Fig. 4.3 The decay of Fourier series coefficients versus the term number.. ............................78 Fig. 4.4 The decay of Fourier series T mn coefficients versus the term number (the value of m used for simulation is from 1 to 10, the value of n used for simulation is from 1 to 10). .......81 Fig. 4.5 The 3-D potential distribution from the device simulator of ISE for DMG SOI MOSFETs device L 1 : L 2 = 1 : 1, y = 0 and V ds = 1V. .............................................................83 Fig. 4.6 The 3-D potential distribution from model results for DMG SOI MOSFETs device L 1 : L 2 = 1 : 1, y = 0 and V ds = 1V............................................................................................83 Fig. 4.7 The 3-D potential distribution from the device simulator of ISE for DMG SOI MOSFETs device L 1 : L 2 = 1 : 3, y = 0 and V ds = 1V..............................................................84 Fig. 4.8 The 3-D potential distribution from model results for DMG SOI MOSFETs device L 1 : L 2 = 1 : 3, y = 0 and V ds = 1V ...........................................................................................84 Fig. 4.9 The 3-D potential distribution from the device simulator of ISE for DMG SOI MOSFETs device L 1 : L 2 = 3 : 1, y = 0 and V ds = 1V..............................................................85 Fig. 4.10 The 3-D potential distribution from model results for DMG SOI MOSFETs device L 1 : L 2 = 3 : 1, y = 0 and V ds = 1V ...........................................................................................85 Fig. 4.11 The 3-D potential distribution from the device simulator of ISE for DMG SOI MOSFETs device L 1 : L 2 = 1 : 1, x = W/2 and V ds = 1V..........................................................86 Fig. 4.12 The 3-D potential distribution from model results for DMG SOI MOSFETs device L 1 : L 2 = 1 : 1, x = W/2 and V ds = 1V. ......................................................................................86 Fig. 4.13 The 3-D potential distribution from the device simulator of ISE for DMG SOI MOSFETs device L 1 : L 2 = 1 : 3, x = W/2 and V ds = 1V..........................................................87 Fig. 4.14 The 3-D potential distribution from model results for DMG SOI MOSFETs device L 1 : L 2 = 1 : 3, x = W/2 and V ds = 1V.. .....................................................................................87 Fig. 4.15 The 3-D potential distribution from the device simulator of ISE for DMG SOI MOSFETs device L 1 : L 2 = 3 : 1, x = W/2 and V ds = 1V..........................................................88 Fig. 4.16 The 3-D potential distribution from model results for DMG SOI MOSFETs device L 1 : L 2 = 3 : 1, x = W/2 and V ds = 1V.. .....................................................................................88 Fig. 4.17 The variation of the surface potential with the normalized channel position for the different ratios of L 1 and L 2 .....................................................................................................90. ix.

(12) Fig. 4.18 The variation of the surface potential with the normalized channel position for the different drain biases................................................................................................................90 Fig. 4.19 The dependence of minimum potential on the gate bias for the different channel lengths. .....................................................................................................................................92 Fig. 4.20 The variation of the electric field with the normalized channel position for the different ratio of L 1 and L 2 ......................................................................................................94 Fig. 4.21 The variation of the electric field with the normalized channel position for the different insulator thicknesses..................................................................................................94 Fig. 4.22 Constant electrostatic potential contours based on the analytical solution (solid curves) for DMG MOSFETs, compared with ISE simulation results (dash curve). Here, V ds = 1V, L=300 nm, and L 1 : L 2 = 1 : 3. .......................................................................................95 Fig. 4.23 Constant electrostatic potential contours based on the analytical solution (solid curves) for DMG MOSFETs, compared with ISE simulation results (dash curve). Here, V ds = 1V, L=300 nm, and L 1 : L 2 = 3 : 1. .......................................................................................96 Fig. 4.24 The dependence of threshold voltage roll-off on the channel length for the different ratios of L 1 and L 2 ..................................................................................................................102 Fig. 4.25 The dependence of threshold voltage roll-off on the channel length for the different gate oxide thicknesses............................................................................................................102 Fig. 4.26(a) 3-D electron density distribution of Y-Z plane for the middle of channel width in the classical case ................................................................................................................104 Fig. 4.26(b) 3-D electron density distribution of Y-Z plane for the middle of channel width in the quantum case................................................................................................................104 Fig. 4.27 The quantum and classical situation of electron density distribution in a vertical cut-line in the middle of the channel......................................................................................105 Fig. 4.28 Drain current simulated in classical and quantum case for the different silicon thicknesses. ............................................................................................................................105 Fig. 4.29 The threshold voltage versus the channel length for the different silicon film thickness in classical and quantum case ................................................................................107 Fig. 4.30 The variation of threshold voltage in classical case and in quantum case for the different silicon thicknesses ...................................................................................................107 Fig. 4.31 The dependence of threshold voltage on channel length in classical case and quantum case..........................................................................................................................108 Fig. 5.1 The subthreshold swing versus the channel length for the different ratios of L 1 and L 2 ............................................................................................................................................112 x.

(13) Fig. 5.2 The subthreshold current versus the gate bias for the different ratios of L 1 and L 2 .115 Fig. 5.3 The subthreshold current versus the gate bias for the different silicon widths ........115 Fig. 5.4 The subthreshold current versus the gate bias for the different gate oxide thicknesses .............................................................................................................................116. xi.

(14) Chapter 1 INTRODUCTION 1.1 MESFETs Devices Overview In recent years, MESFETs have received more attention than MOSFETs in the high speed or high frequency applications [1-2]. Compared with MOSFETs, SOI MESFETs have several superior electrical characteristic such as better isolation between source (drain) and substrate, less mobility degradation, immunity to hot-carrier effect, and better radiation hardness [3-5]. By using a Schottky barrier as the gate electrode and two ohmic contacts as the source and drain electrodes, it form MESFET. Most MESFET are made of n-type silicon or III-V compound semiconductors because of the high electron mobility. Of particular important is GaAs, because its electron mobility is better than silicon. In the following, two important GaAs logic are presented. The simplest and most widely used enhancement/depletion mode GaAs logic family is the direct coupled FET logic (DCFL) circuit [8]. Schematics of a DCFL inverter and NOR gate are shown in Fig. 1.1. The DCFL inverter consists only of an enhancement MESFET (EMESFET) connected to the power supply via pull-up depletion MESFET (DMESFET). This configuration is very similar to that of E/D NMOS logic circuits.. 1.

(15) (a). (b). Fig. 1.1 Schematics of DCFL (a) Inverter (b) 3-input NOR gate [8].. On the other hand, it has been reported that the application of dual-material gate (DMG) MESFET introduces step potential at the interface between the different gate materials and make the more uniform field in the channel region that enhances the carrier transit speed and hence increases the device driving capability [9-10]. In this thesis, three-dimensional (3-D) Poisson equation has been developed by superposition method. The 3-D SOI-MESFETs model explores narrow width effect that is superior to two-dimensional (2-D) model. The cross section of the device used in this study is schematically as shown in Fig. 1.2. Device parameters used for simulating are t si =40 nm, t ox =50 nm, W=50 nm, and L=100 nm. Fig. 1.2 also shows the electron distribution in the channel. We can find that the current carrying electrons are tightly confined to the interface between the channel and buried oxide. The larger MESFET mobility than MOSFET is attributed to the reduced role of interface roughness scattering. Fig. 1.3 shows that the electrons in the MESFET are located closed to the buried oxide. The fact that the current carrying channel in the MESFET is further away from the top gate is one of. 2.

(16) reasons why the MESFET shows an increased mobility compared to the MOSFET [11]. Fig. 1.4 shows the variation of the bottom potential with the normalized channel position for different drain biases. It is shown that the drain-induced barrier lowering (DIBL) effect for Dual-Material Gate (DMG) is better than Single-Material Gate (SMG) devices. Fig. 1.5 shows the electric field in the channel of SMG and DMG devices. It is shown that the maximum electric field near the drain for DMG is smaller than SMG structures, which can effectively screen the hot-carrier effect occurring near the drain side. Fig. 1.6 shows electrostatic potential contours for SMG device and there is only vertical electric field in it. Fig. 1.7 shows electrostatic potential contours for DMG device. The contour under the material 1 (M 1 ) induces vertical electric field that can control threshold behavior. However, the contour in the material 2 (M 2 ) induces horizontal electric field that can absorb the electric field from the variation of the drain side and completely suppress the DIBL.. 3.

(17) Electron Concentration (E+1016 /cm3). Fig. 1.2 ISE simulation results of MESFET for the electron distributions.. 25 . 20. ISE: Nd=1017 cm-3 tsi= 40 nm tox= 50 nm W= 80 nm L= 300 nm. 15 10 5 0 0. 10 20 30 Silicon Thickness, tsi (nm). 40. Fig. 1.3 Variation of the electron concentration along the channel thickness for the MESFET at V ds =1.0V.. 4.

(18) Bottom Potential Y(W/2, tsi, z) (V). tox= 300 nm tsi= 40 nm W= 150 nm Nd= 1017 cm-3 Vgs= 0 V eV eV L1=L2= 250 nm. 1.5 1 0.5. DMG-MESFET SMG-MESFET. Vds = 1.0 V. Vds = 0.5 V. 0 -0.5 0. 0.2 0.4 0.6 0.8 Normalized Channel Position (z/L). 1. Fig. 1.4 ISE simulation results of SMG and DMG devices for the bottom potential.. Electric Field, E(|E|â106 V/cm). 5 tox= 300 nm tsi= 40 nm W= 150 nm Nd= 1017 cm-3 Vds= 1.0 V L= 500 nm. 4 3. DMG-MESFET SMG-MESFET. 2 1 0 0. 0.2 0.4 0.6 0.8 Normalized Channel Position (z/L). Fig. 1.5 ISE simulation results of SMG and DMG devices for the electric field.. 5. 1.

(19) Normalized Channel Height Position ( y/tsi ). 0 -0.356 V. 0.2. -0.306. 0.4. -0.258. 0.6. -0.203. 0.8. -0.157 -0.103 -0.056 0.003 0.043 0.092. 1 0. 0.2 0.4 0.6 0.8 Normalized Channel Length Position ( z/L ). 1. Fig. 1.6 ISE simulation results of SMG device for the potential contours. Device. Normalized Channel Height Position ( y/tsi ). parameters are t si =40 nm, t ox =300 nm, W=150 nm, and L=500 nm.. 0 0.107. -0.368 V. 0.2. -0.331 0.143 -0.287. 0.4. 0.188. -0.256. 0.6 0.8. -0.192. 0.213. -0.162. 0.241. -0.124 -0.105 -0.062. 0.276 0.309. 1 0. 0.2 0.4 0.6 0.8 Normalized Channel Length Position ( z/L ). 1. Fig. 1.7 ISE simulation results of DMG device for the potential contours. Device parameters are t si =40 nm, t ox =300 nm, W=150 nm, and L 1 =L 2 =250 nm. 6.

(20) 1.2 MOSFETs Devices Overview The metal-oxide-semiconductor-field-effect transistor (MOSFET) is the building block of VLSI circuits in microprocessors and dynamic memories. In keeping with the progress in process technology, CMOS devices have been scaled down, continuously pushing the MOS technology into the deep-submicrometer era. The circuit diagram of a single CMOS inverter is shown in Fig. 1.7(a) and Fig. 1.7(b). Assuming that the input signal has been sufficiently long on logic low (V in =V ss =0V), both the n-FET and the p-FET have reached steady state conditions. Due to the low input, the p-FET channel is opened while the n-FET is switched off. Applying a step function to the input (V in (t=0+)=V dd ) turns off the p-FET and the n-FET is switched on. Now the n-FET has to discharge the common node, finally pulling the output voltage V out down to zero. The down propagation delay τ can be measured at the point where V out = V dd /2, which characterizes the n-FET dominated switching performance from output high to low [9].. (a). (b). Fig. 1.8 (a) Circuit diagram of a CMOS inverter. (b) Output voltage response applying a step function at the input [9].. 7.

(21) With the advancement of the gate material, DMG MOSFETs has become a promising candidate to suppress the short channel effects (SCEs) and enhance the carrier transport efficient [10]. In a DMG MOSFET, the work function of metal gate1 (M 1 ) is greater than metal gate2 (M 2 ) for an n-channel MOSFET. It will induce the step potential and make a peak electric field in the interface that improves the carrier transit speed. Owing to the screen effects from the device, the high electric field near the drain side can be effectively reduced, which suppresses the hot carrier effects (HCEs) and enhance the device reliability. 2-D model for DMG MOSFET had been demonstrated in recent years [11-15]. However, the effects of the 3-D DMG structure have not been studied so far in the case of SOI MOSFETs, which plays an important role in the present CMOS design. In this thesis, an analytical model for SOI MOSFET is presented by solving the 3-D Poisson equation. The model results are verified by comparing them with the simulated results from ISE-TCAD [16]. Besides giving a physical insight into the device physics, the model provides guidance for the basic design for the short-channel DMG SOI MOSFETs. The cross section of the device used in this study is schematically shown in Fig. 1.9. Device parameters used for simulating are t si =40 nm, t ox1 =5 nm, t ox2 =50 nm, W=50 nm, and L=100 nm. Fig. 1.9 also shows the electron distribution in the channel. In the MOSFET, the current carrying electrons are tightly confined to the upper Si/SiO 2 interface. Fig. 1.10 shows the electrons in the MOSFET are located closed to the top SiO 2 layer [9]. Fig. 1.11 shows the variation of the surface potential with the normalized channel position for different drain biases. It is also shown that the minimum potential for DMG device is larger and shifting toward the source than SMG devices. Fig. 1.12 shows the electric field in the channel of SMG and DMG devices. It is shown that the maximum electric field near the drain for DMG is smaller than SMG structures. Fig. 1.13 shows electrostatic potential contours for SMG device 8.

(22) and there is only vertical electric field in it. Fig. 1.14 shows electrostatic potential contours for DMG device. The contour under the M 1 has vertical electric field that can control threshold behavior. However, the contour in the M 2 has horizontal electric field that can absorb the electric field from the variation of the drain side and completely suppress the DIBL.. 9.

(23) Electron Concentration (E+1016 /cm3). Fig. 1.9 ISE simulation results of MOSFET for the electron distributions.. 25 . 20. ISE: Na=1017 cm-3 tox1= 5 nm tox1= 5 nm tsi= 40 nm W= 80 nm L= 300 nm. 15 10 5 0 0. 10 20 30 Silicon Thickness, tsi (nm). 40. Fig. 1.10 Variation of the electron concentration along the channel thickness for the MOSFET at V ds =1.0V.. 10.

(24) Surface Potential Y(W/2, 0, z) (V). 2.5 tox1= 5 nm tox2= 50 nm tsi= 40 nm W= 80 nm Nd= 1017 cm-3 Vgs= 0 V eV eV L1=L2= 150 nm. 2 1.5 1. DMG-MOSFET SMG-MOSFET. Vds = 1.0 V. Vds = 0.5 V. 0.5 0 0. 0.2 0.4 0.6 0.8 Normalized Channel Position (z/L). 1. Fig. 1.11 ISE simulation results of SMG and DMG devices for the surface potential.. Electric Field, E(|E|â106 V/cm). 1.2 tox1= 5 nm tox2= 50 nm tsi= 40 nm W= 80 nm Nd= 1017 cm-3 Vgs= 0 V eV eV L1=L2= 150 nm. 0.8. DMG-MESFET SMG-MESFET. 0.4. 0 0. 0.2 0.4 0.6 0.8 Normalized Channel Position (z/L). Fig. 1.12 ISE simulation results of SMG and DMG devices for the electric field.. 11. 1.

(25) Normalized Channel Height Position ( y/tsi ). 0 -0.166 V -0.137 -0.108 -0.078 -0.049 -0.019 0.007 0.039. 0.2 0.4 0.6. 0.063 0.094. 0.8. 0.126 0.155 0.187. 1 0. 0.2 0.4 0.6 0.8 Normalized Channel Length Position ( z/L ). 1. Fig. 1.13 ISE simulation results of SMG for the potential contours. Device parameters. Normalized Channel Height Position ( y/tsi ). are t si =40 nm, t ox1 =5 nm, t ox2 =50 nm, W=80 nm, and L=300 nm.. 0 -0.137 V. 0.213. -0.111. 0.259 0.297. 0.2. -0.072. 0.4. -0.047 -0.021 0.006. 0.317 0.331. 0.032. 0.6. 0.065 0.092 0.127 0.142. 0.8. 0.171. 1 0. 0.2 0.4 0.6 0.8 Normalized Channel Length Position ( z/L ). 1. Fig. 1.14 ISE simulation results of DMG device for the potential contours. Device parameters are t si =40 nm, t ox1 =5 nm, t ox2 =50 nm, W=80 nm, and L 1 =L 2 =150 nm. 12.

(26) Chapter 2 THREE DIMENSIONAL POTENTIAL AND THRESHOLD VOLTAGE MODEL FOR DUAL-MATERIAL GATE SOI MESFETs 2.1 Model Derivation A perspective view of a DMG SOI MESFETs is illustrated in Fig. 2.1.The top gates include dual materials M 1 and M 2 . The impurity density in the channel region is uniform and the source and drain are highly doped. According to 3-D Poisson equation, the bottom potential of silicon body can be written as [9] [18].  2 i  x, y, z   2 i  x, y, z   2 i  x, y, z  qN     d i  1, 2 2 2 2 x y z  si.  0  x  W , 0  y  tsi , 0  z  L1  L2 . Drain z n+. M2. Gate. n M1 (0,0,0) tsi. n+. L2 x L1. y Source. tox W Sub. Fig. 2.1 The 3-D structure for DMG SOI MESFETs. 13. (2.1).

(27) Where N d is the uniform film doping concentration independent of the gate length,  si is the dielectric constant of silicon, t si is the film thickness, t ox is the back oxide thickness, W is the device channel width, L is the device channel length, the y-axis is vertical to the channel thickness, the x-axis is parallel to the channel width and z-axis presents the channel length, respectively. Where i=1 and i=2 signify the regimes under the gate material 1 and gate material 2. By using the superposition method to solve eq. (2.1), the resultant solution  i ( x, y, z ) can be divided into three parts, 1-D potential solution V i (y), 2-D potential solution U i (x,y) and 3-D potential solution  i (x,y,z) at eq. (2.2), which satisfy the following 1-D Poisson equation, 2-D Laplace equation and 3-D Laplace equation, respectively[2-3]..  i  Vi  y   U i  x, y   i  x, y, z  i  1, 2  0  x  W , 0  y  tsi , 0  z  L1  L2  (2.2) Substituting eq. (2.2) into eq. (2.1), we obtain.  2U i  x, y   2i  x, y, z   2Vi  y   2U i  x, y   2i  x, y, z   2i  x, y, z  qN + +  + +  d 2 2 2 2 2 2  si x x y y y z (2.3) 1-D Poisson equation  2Vi ( y ) qN d  i  1, 2 y 2  si. (2.4). 2-D Laplace equation  2U i ( x, y )  2U i ( x, y ) +  0 i  1, 2 x 2 y 2. (2.5). 3-D Laplace equation  2i ( x, y,z)  2i ( x, y,z)  2i ( x, y,z) + + = 0 i  1, 2 x 2 y 2 z 2 14. (2.6).

(28) 2.2 3-D Boundary Conditions Value Problem Since we have two regions in the front gate of the SOI MESFETs structure, the bottom potential under M 1 and M 2 can be written based on eq. (2.2) as.  1  V1  y   U1  x, y   1  x, y, z .  0  x  W , 0  y  tsi , 0  z  L1 . (2.7).  2  V2  y   U 2  x, y   2  x, y, z .  0  x  W , 0  y  tsi , L1  z  L1  L2 . (2.8). To solve for the Poisson equation, the following boundary conditions are needed.. (a) At the top side, potential of the silicon body for M 1 and M 2 for the DMG SOI MESFETs can be expressed as[16] [18].  1  x,y  0, z   Vgs   bi1.  0  x  W , 0  z  L1 .  2  x,y  0, z   Vgs   bi 2.  0  x  W , L1  z  L1 +L2 . (2.9) (2.10). Where Φ bi1 and Φ bi2 are the built-in voltage of the schottky barrier at gate1 and gate2, those can be obtained by the difference between the metal work function and the electron affinity of the semiconductor. Therefore, the schottky barrier of the M 1 and M 2 at the top gate must be different and they are given as Fbi1 = fM 1 - fsi. (2.11). Fbi 2 = fM 2 - fsi. (2.12).  si is the silicon work function, which is given by. fsi = csi + 15. Eg 2q. - fB. (2.13).

(29) Where E g is the silicon band-gap at room temperature 300 K,  si is the electron affinity of silicon,  B = V T ln(N d / n i ) is the Fermi potential, V T is the thermal voltage, n i is the intrinsic carrier concentration, and q is elementary charge.. (b) At the bottom side, electric flux at the interface of silicon/back oxide is continuous for both gates..  1  x, y,z  y.  2  x, y,z  y. y tsi. y tsi. . .  ox Vbs  V fb  1  x, y  tsi ,z    0  x  W , 0  z  L1  (2.14) tox  si.  ox Vbs  V fb  2  x, y  tsi ,z    0  x  W , L1  z  L1 +L2  (2.15) tox  si. Where V bs is the substrate to source voltage, V fb is the flat-band voltage of SiO 2 , t si is the thickness of the active silicon film, t ox is the thickness of the back oxide layer,.  si is permittivity of silicon, and  ox is permittivity of silicon. ( si =11.78.8510-14,  ox =3.98.8510-14) (c) The junction potential at the interface of the two different gate materials of the top gate is continuous..  1  x, y , z  L1    2  x, y , z  L1 .  0  x  W , 0  y  tsi . (2.16). (d) The junction electric flux at the interface of two different materials of the top gate is continuous..  1  x, y, z   2  x, y, z   z z zL zL 1. 1. 16.  0  x  W , 0  y  tsi . (2.17).

(30) (e) The potential at the source end is.  1  x, y, z  0   Vbi.  0  x  W , 0  y  tsi . (2.18). (f) The potential at the drain end is.  2  x, y, z  L1  L2   Vbi  Vds.  0  x  W , 0  y  tsi . (2.19).  0  y  tsi , 0  z  L1  L2 . (2.20). (g) The potential at the front side is[19].  1  x  0, y, z    2  x  0, y, z   Vbi. (h) The potential at the back side is[19].  1  x  W , y, z    2  x  W , y, z   Vbi.  0  y  tsi , 0  z  L1  L2  (2.21). Where V bi = V T ln(N a / N d ) is the built-in voltage between the channel to source (drain) junction and channel and V ds is the drain-source voltage[22].. 17.

(31) 2.3 1-D Solution From boundary conditions (a) and (b), we can get four equations for satisfying 1-D Poisson equation.. V1  y  0   Vgs   bi1. (2.22). V2  y  0   Vgs   bi 2. (2.23). V1  y  y V2  y  y. .  ox Vbs  V fb  V1  y  tsi   tox  si. (2.24). .  ox Vbs  V fb  V2  y  tsi   tox  si. (2.25). y tsi. y  tsi. 1-D solution can be obtained separately under the two regions M 1 and M 2 using the eq. (2.4). V1  y   . qN d 2 y  a1 y  b1 2 si. (2.26). qN d 2 y  a2 y  b2 2 si. (2.27). V2  y   . From eq. (2.22) and eq. (2.24), 1-D coefficients a 1 and b 1 can be solved as. a1 . 2   bi1  Vbs  V fb  Vgs   ox   si +q  N d  tsi  tsi   ox  2  tox   si  2   si  tsi   ox   si  tox . b1  Vgs   bi1. (2.28). (2.29). From eq. (2.23) and eq. (2.25), 1-D coefficients a 2 and b 2 can be solved as. a2 . 2   bi 2  Vbs  V fb  Vgs   ox   si +q  N d  tsi  tsi   ox  2  tox   si  2   si  tsi   ox   si  tox . b2  Vgs   bi 2. (2.30). (2.31) 18.

(32) From eqns. (2.28-2.31), 1-D complete solution can be shown as  qN V1  y     d  2 si.  2  2   bi1  Vbs  V fb  Vgs   ox   si +q  N d  tsi  tsi   ox  2  tox   si     y  Vgs   bi1    y    2   si  tsi   ox   si  tox    . (2.32) and  2   bi 2  Vbs  V fb  Vgs   ox   si +q  N d  tsi  tsi   ox  2  tox   si    qN    y  Vgs   bi 2  V2  y     d   y 2     2   si  tsi   ox   si  tox   2 si   . (2.33). 19.

(33) 2.4 2-D Coefficients Solution By using separation method with boundary conditions, we obtain the following resultant solution of the 2-D Laplace equation for M 1 and M 2 . . . .  0  x  W , 0  y  tsi . (2.34). . .  0  x  W , 0  y  tsi . (2.35). U1 ( x, y )   Pn e kn x  Qn ekn x sin  kn y  n 1. and . U 2 ( x, y )   Rn e  kn x  S n e kn x sin  kn y  n 1. From boundary conditions (g) and (h), we get four equations for satisfying 2-D Laplace equation.. V1  y   U1  0, y   Vbi. (2.36). V1  y   U1 W , y   Vbi. (2.37). V2  y   U 2  0, y   Vbi. (2.38). V2  y   U 2 W , y   Vbi. (2.39). Substituting eq. (2.34) into eqns. (2.36-2.37) and eq. (2.35) into eqns. (2.38-2.39), the Fourier series coefficients of P n , Q n , R n, and S n can be obtained as. Cn eknW  Cn 2Sinh  knW . (2.40). Cn e knW  Cn Qn  2Sinh  knW . (2.41). Pn . Rn . Dn eknW  Dn 2Sinh  knW . 20. (2.42).

(34) Sn .  Dn e knW  Dn 2Sinh  knW . (2.43). with. Cn . Dn . qN d     a1     Vbi  b1   2 si. (2.44). qN d     a2     Vbi  b2   2 si. (2.45). . . Whereα,ζ,σand  in above equations are defined as.  . 2kn tsi  sin  2kntsi  4k n. (2.46). 2  2 cos  kn tsi   kntsi  2sin  kn tsi   cos  kn tsi  kn tsi . . kn 3. sin  kntsi   cos  kn tsi  kntsi kn 2. . (2.47). (2.48). 1  cos  kntsi  kn. (2.49). Where k n is the eigen value which satisfies the equation tan(kntsi ) = -. esi tox kn eox. (2.50). Fig. 2.2 shows the decay of Fourier series P n and R n coefficients versus the term number. We can find that when term number n is larger than 10, the Fourier series coefficients decay smoothly and its values approach zero. Since the coefficients decay so fast, the first term of P n and R n will dominate the whole series and be used to derive the threshold voltage and subthreshold swing according to the minimum bottom potential [23].. 21.

(35) 1.2. Coefficient (Pn , Rn ). :Pn :Rn. tox = 300 nm W = 150 nm tsi = 40 nm Vds = 1.0 V Nd = 1017 cm-3 M1= 5.04 eV. 0.8. M2= 4.54 eV L1 = L2 = 250 nm. 0.4. 0 0. 3. 6. 9 12 15 Term Number, n. 18. 21. 24. Fig. 2.2 The decay of Fourier series P n and R n coefficients versus the term number.. 22.

(36) 2.5 3-D Laplace Equation Solution By using separation method together with boundary condition, one obtains the following resultant solution of the 3-D Laplace equation. From eq. (2.6), we let.   x, y,z   X  x   Y  y   Z  z . (2.51). Substitute eq. (2.51) into eq. (2.6) to obtain X ''  x   Y  y   Z  z   X  x   Y ''  y   Z  z   X  x   Y  y   Z ''  z   0. (2.52). Eq. (2.52) divided by X ( x)Y ( y ) Z ( z ) , it leads to X ''  x  Y ''  y  Z ''  z  + + =0 X ( x) Y  y  Z  z . (2.53). By letting the following equations, X ''  x  Y ''  y  Z ''  z   k12 ,   k2 2 ,  k12  k2 2 X  x Y  y Z  z. (2.54). We obtain. X  x   a1cos  k1 x   a2 sin  k1 x . (2.55). Y ( y )  a3cos  k2 y   a4 sin  k2 y . (2.56). Z  z   a5e. . . . k12  k22 z.  a6 e. . . k12  k22 z. (2.57). The 3-D potential distribution for M 1 and M 2 can be obtained as . 1  x, y,z    a1cos  k1 x   a2 sin  k1 x    a3cos  k2 y   a4 sin  k2 y    a5e. . . . k12  k22 z. .  a6 e. . . k12  k22 z.   . (2.58) . 2  x, y,z    a7 cos  k3 x   a8 sin  k3 x    a9 cos  k4 y   a10 sin  k4 y    a11e . . . . k3 2  k 4 2 z.  a12 e. . . k3 2  k 4 2 z.   . (2.59). 23.

(37) Due to 1  x, 0, z   0 and 2  x, 0, z   0 as boundary condition of (a), the coefficients in eq. (2.58) and eq. (2.59) are expressed as a3  a9  0. (2.60). Due to 1  0, y, z   0 and 2  0, y, z   0 as boundary condition of (g) the other coefficients in eq. (2.58) and eq. (2.59) are expressed as a1  a7  0. (2.61). From boundary condition of (h), the eigen values in eq. (2.58) and eq. (2.59) can be obtained. k1  k3 . m , m  1, 2,3... W. (2.62). Substituting eqns. (2.60-2.62) into eqns. (2.58-2.59), one obtains . 1  x, y,z   a2 sin  k1 x   a4 sin  k2 y    a5 e. . . k12  k2 2 z. . . . .  a6 e. . . k12  k2 2 z.   . (2.63). and . 2  x, y,z   a8 sin  k3 x   a10 sin  k4 y    a11e . . k3 2  k 4 2 z.  a12 e. . . k32  k42 z.   . (2.64). Using a3cos (k2 y )  a4 sin(k2 y )  a32  a42 sin  k2 y  , eqns. (2.59-2.60) can be rewritten as . . 1  x, y,z    Tmn e k n 1 m 1. . mn z. . mn z. .  Bmn ekmn z sin  km x  sin  kn y .  0  x  W , 0  y  tsi , L1  z  L1  L2 . m  m  2 , and kmn     kn . W W  2. where km . (2.65).  0  x  W , 0  y  tsi , 0  z  L1 . 2  x, y,z     Amn e k n 1 m 1. .  U mn e kmn z sin  km x  sin  kn y . 24. (2.66).

(38) From boundary condition of (a), one obtains 1  x, y, z  y 2  x, y, z  y. .  ox 1  x, y  tsi , z   tox  si. (2.67). .  ox 2  x, y  tsi , z   tox  si. (2.68). y  tsi. y  tsi. Using eq. (2.67) and eq. (2.68), we obtain tan  kn tsi  .  si tox kn. (2.69).  ox. Where the Fourier series coefficients of T mn , U mn , A mn and B mn in the eqns. (2.65-2.66) are expressed as Tmn . U mn . e. e. Bmn . F. n. e.  Emn C osh  kmn L1    Gn  Emn e kmn L1 Sinh  kmn  L1  L2  . (2.70).  Emn C osh  kmn L1    Gn  Emn e  kmn L1 Sinh  kmn  L1  L2  . (2.71). n.  kmn  L1  L2 . Amn . F. kmn  L1  L2 . kmn  L1  L2 . e. 2Sinh  kmn  L1  L2  . 2Sinh  kmn  L1  L2  . F. n.  Emn C osh  kmn L1    Gn. (2.72). 2Sinh  kmn  L1  L2    kmn  L1  L2 . F. n.  Emn C osh  kmn L1    Gn. (2.73). 2Sinh  kmn  L1  L2  . with Fn . Emn . Gn . . 2  2   2  1   2 km m. . (2.74). . (2.75). . (2.76).  m. . 2 1  1  1  1km m.  m. . 2 3  3  1   3 km m.  m. 25.

(39) Where 1 ,  2 , 3 , 1 ,  2 ,  3 and  in above equations are defined as. . 2kn tsi  sin  2kntsi  4k n. (2.77). 1   a2  a1      b2  b1  . (2.78). 2 . qN d     a1     Vbi  b1   2 si. (2.79). 3 . qN d     a2     Vbi  Vds  b2   2 si. (2.80). km  Rn  Sn  Pn  Qn   km  1  Rn  Pn   e knW   Sn  Qn   eknW  1  2 kmn. (2.81). km  Pn  Qn   km  1  Pn  e knW  Qn  eknW  2  2 kmn. (2.82). km  Rn  Sn   km  1  Rn  e knW  Sn  eknW  3  2 kmn. (2.83). m. m. m. . 2  2 cos  kn tsi   kntsi  2sin  kn tsi   cos  kn tsi  kn tsi .  . kn 3. sin  kntsi   cos  kn tsi  kntsi kn 2. (2.84). (2.85). 1  cos  kntsi  kn. (2.86). 26.

(40) Fig. 2.3 shows the decay of Fourier series T mn coefficients versus the term number. Since the Fourier series coefficients decay rapidly, the first term of T mn (i.e., T mn= T 11 ) will dominate the whole series and can be used to derive the threshold voltage and subthreshold swing according to the minimum surface potential [24-25].. 1.2 tox= 300 nm W= 150 nm tsi = 40 nm Nd= 1017 cm-3 Vgs= 0 V Vds= 1.0 V eV eV L1 = L2 L= 500 nm. Coefficient (Tmn). 1 0.8 0.6 0.4 0.2 0 -0.2 0. 20. 40 60 Term Number, mn. 80. 100. Fig. 2.3 The decay of Fourier series T mn coefficients versus the term number (the value of m used for simulation is from 1 to 10, the value of n used for simulation is from 1 to 10).. 27.

(41) 2.6 3-D Generalized Potential Model The full expression for M 1 and M 2 in silicon channel region is.  1  x, y, z   V1  y   U1  x, y   1  x, y, z  .  qN d  y 2  a1  y  b1   Pn e  kn x  Qn e kn x sin  kn y  2 si n 1. . . . . . (2.87). .   Tmn e  kmn z  U mn e kmn z sin  km x  sin  kn y  n 1 m 1. and.  2  x, y, z   V2  y   U 2  x, y   2  x, y, z  .  qN d  y 2  a2  y  b2   Rn e kn x  Sn ekn x sin  kn y  2 si n 1. . . . . . (2.88). .   Amn e  kmn z  Bmn ekmn z sin  km x  sin  kn y  n 1 m 1. To verify the analytical potential model, the 3-D potential distribution by 3-D simulator of ISE is compared with the model solution at different cross-section with x= W/2 and y=t si [15]. Fig. 2.4 -2.9 show the 3-D bottom potential distribution from the device simulator and model results with the same device structure at y=t si and the same drain bias V ds = 1V for different ratios of L 1 and L 2. Fig. 2.10 -2.15 show the 3-D potential distribution from the device simulator and model results with the same device structure at x=W/2 and the same drain bias V ds = 1V for different ratios of L 1 and L 2. The good agreement between the results calculated from our 3-D potential model with those simulated from device simulator is obtained.. 28.

(42) Fig. 2.4 The 3-D potential distribution from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, y = t si and V ds = 1V.. Fig. 2.5 The 3-D potential distribution from model results for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, y = t si and V ds = 1V.. 29.



(45) Fig. 2.10 The 3-D potential distribution from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, x = W/2 and V ds = 1V.. Fig. 2.11 The 3-D potential distribution from model results for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, x = W/2 and V ds = 1V.. 32.



(48) Fig. 2.16 shows the variation of the bottom potential with the normalized channel position for different combinations of gate lengths L 1 and L 2 . With keeping the sum of total gate length (L 1 + L 2 ) to be constant as indicated in Fig. 2.16, Fig. 2.17 shows the variation of the bottom potential with the normalized channel position for different silicon thicknesses. Fig. 2.18 shows the variation of the bottom potential with the normalized channel position for different drain biases. The simulated results for SMG SOI MESFETs are also included for comparison. It can be observed that the DMG structure with the screen gate of low work function, the variation of drain potential with the position near the drain voltage is efficiently absorbed which causes the smaller electric field for DMG MESFETs than that for SMG MESFETs and effectively reduces the HCEs. Fig. 2.19 shows the variation of the bottom potential with the normalized channel position for different work functions.. 35.

(49) Bottom Potential Y(W/2, tsi, z) (V). 1.5. tox= 300 nm W= 150 nm Nd= 1017 cm-3 Vgs= 0 V Vds= 1.0 V eV eV L= 500 nm. 1. 0.5. Symbol : Model Solid line : ISE  L1 : L2 = 1 : 3  L1 : L2 = 1 : 1  L1 : L2 = 3 : 1. 0. -0.5. -1 0. 0.2. 0.4. 0.6. 0.8. 1. Normalized Channel Position (z/L) Fig. 2.16 The variation of the bottom potential with the normalized channel position for the different ratios of L 1 and L 2 .. Bottom Potential Y(W/2, tsi, z) (V). 1.5. tox= 300 nm W= 150 nm Nd= 1017 cm-3 Vgs= 0 V Vds= 1.0 V eV eV L= 500 nm. 1. 0.5. Symbol : Model Solid line : ISE  tsi = 20 nm  tsi = 40 nm  tsi = 60 nm. 0. -0.5. -1 0. 0.2. 0.4. 0.6. 0.8. 1. Normalized Channel Position (z/L) Fig. 2.17 The variation of the bottom potential with the normalized channel position for the different silicon thicknesses.. 36.

(50) Bottom Potential Y(W/2, tsi, z) (V). 2. tox= 300 nm W= 150 nm Nd= 1017 cm-3 Vgs= 0 V eV eV L1 = L2 L = 500 nm. 1. Symbol : Model Solid line : DMG ISE Dot line : SMG ISE. Vds = 1.5 V Vds = 1.0 V Vds = 0.5 V. 0. -1 0. 0.2. 0.4. 0.6. 0.8. 1. Normalized Channel Position (z/L) Fig. 2.18 The variation of the bottom potential with the normalized channel position for the different drain biases.. Bottom Potential Y(W/2, tsi, z) (V). 1.5. tox= 300 nm tsi= 40 nm W = 150 nm Nd= 1017 cm-3 Vgs= 0 V Vds= 1.0 V eV L= 500 nm. 1. 0.5. Symbol : Model Solid line : ISE.  eV  eV  eV. 0. -0.5. -1 0. 0.2. 0.4. 0.6. 0.8. 1. Normalized Channel Position (z/L) Fig. 2.19 The variation of the bottom potential with the normalized channel position for the different work functions.. 37.

(51) 2.7 Minimum Channel Potential The DIBL effect of the short-channel SOI MESFETs may be demonstrated by observing the bottom potential   x, y, z  given in eqns. (2.87-88). Since the subthreshold leakage current often occurs at the position of the minimum channel bottom potential, the DIBL effect on the device behavior in the subthreshold region may be monitored by the minimum bottom potentialΨ min . Due to rapid decay of the Fourier series coefficients as shown in eq. (2.40), eq. (2.41), eq. (2.70) and eq. (2.71), the first term of them can dominate the whole series. From eq. (2.83), the minimum potential can be derived by setting.  1 ( x, y, z )  1 ( x, y, z )  0 and  0 . The x z. position x min and z min of the minimum channel potential can be found by P1 Q1  2kn 1 ln. xmin. T11 U11  2k11. (2.89). ln. zmin. (2.90). When x min and z min are solved, the minimum channel potential  1,min for the DMG MESFETs can be obtained as.  1,min . qN d  tsi 2  a1  tsi  b1  2 PQ 1 1 sin  kn 1t si   2 T11U11 sin  km 1 xmin  sin  kn 1t si  2 si (2.91). Fig. 2.20 shows the dependence of minimum bottom potential on the gate bias ranges between -0.3 to 0.3 voltages for different channel length. The subthreshold leakage current is stronger for short-channel length (L < 100 nm), and it leads to threshold voltage roll-off. Besides, the DIBL increases for the shorter channel. 38.

(52) length[26]. Fig. 2.21 shows the dependence of minimum channel potential on the gate bias for the different silicon thickness.. Minimum Potential Ymin ( V ). 0.2 0. L = 500 nm L = 300 nm L = 100 nm. Symbol : ISE Solid line : Model. -0.2 -0.4 tsi = 40 nm Vds = 1.0 V tox = 300 nm W = 150 nm M1= 5.04 eV Nd = 1017 cm  = 4.54 eV M2 L1 = L2. -0.6 -0.8 -0.3. -0.2. -0.1 0 0.1 Gate Bias, VGS ( V ). 0.2. 0.3. Fig. 2.20 The dependence of minimum potential on the gate bias for the different the cannel lengths.. 39.

(53) Minimum Potential Ymin ( V ). 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 -1.1 -1.2 -0.3. tsi = 20 nm tsi = 40 nm tsi = 60 nm. Symbol : ISE Solid line : Model. W = 150 nm Vds = 1.0 V M1= 5.04 eV M2= 4.54 eV L1 = L2= 250 nm Nd = 1017 cm-3. -0.2. -0.1 0 0.1 Gate Bias, VGS ( V ). 0.2. 0.3. Fig. 2.21 The dependence of minimum potential on the gate bias for the different silicon thicknesses.. 40.

(54) 2.8 Electric Field and Potential Contour From eq. (2.83) and eq. (2.84), the electric field can be derived by the partial derivative of  1  x, y, z  and  2  x, y, z  with respect to z. Then electric field of the silicon body for M 1 and M 2 for the DMG SOI MESFETs can be expressed as . . . .  0  z  L1 . (2.92). . .  L1  z  L1  L2 . (2.93). E1   Tmn e  kmn z  U mn e kmn z kmn sin  km x  sin  kn y  n 1 m 1. . . E2    Amn e  kmn z  Bmn ekmn z kmn sin  km x  sin  kn y  n 1 m 1. Fig. 2.22 shows the lateral electric field distribution along the channel for different ratios of L 1 and L 2 . It is revealed that DMG structure induces the peak electric fields within the interface of L 1 and L 2 . In comparison to the DMG MESFET, it is obviously observed that the DMG MESFET has the lower electrical field near the drain side than SMG MESFET and can decrease the impact ionization and HCEs [27]. Fig. 2.23 and Fig. 2.24 show the 3-D electric field from the device simulator and model results with the same device structure at y=t si and V ds = 1V for L 1 equal to L 2. Besides the electric field, potential contour is shown in Fig. 2.25. It shows constant electrostatic potential contours based on the analytical solution (solid curves) for DMG MESFETs, compared with ISE simulation results (dash curve) and excellent agreements are observed. The potential contours under the gate of M 1 with high work function tend to bend vertically, which implies that the electric fields from the gate of M 1 can easily penetrate into the channel and control the threshold behavior. (M 1 is so-called control gate) [26]. On the other hand, the potential contours in the gate of M 2 with low work function tend to bend laterally and readily absorb the electric field from the variation of the drain potential and completely suppress the DIBL behavior (M 2 is so-called screen gate) [26]. 41.

(55) Electric Field , E ( |E|¥106 V/cm ). tox = 300 nm tsi = 40 nm Vgs = 0 V Vds = 1.0 V Nd = 1017 cm-3 M1= 5.04 eV. 0.4. 0.3. Symbol : Model Solid line : ISE Dot Line : SMG. M2= 4.54 eV L = 500 nm. 0.2.  L1. : L2 = 1 : 3.  L1. : L2 = 1 : 1.  L1. : L2 = 3 : 1. 0.1. 0 0. 0.2 0.4 0.6 0.8 Normalized Channel Position ( z/L ). 1. Fig. 2.22 The variation of the electric field with the normalized channel position for the different ratios of L 1 and L 2 .. 42.

(56) Fig. 2.23 The 3-D electric field from the device simulator of ISE for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, y = t si and V ds = 1V.. Fig. 2.24 The 3-D electric field from model result for DMG SOI MESFETs device L 1 : L 2 = 1 : 1, y = t si and V ds = 1V.. 43.

(57) Normalized Channel Height Position ( y/tsi ). 0 ISE Model 0.469. 0.2. 0.594. 0.4 -0.281 Volts. 0.719. -0.156. 0.6. 0.844. -0.031 0.094. 0.8. 0.219 0.344. 1 0. 0.2 0.4 0.6 0.8 Normalized Channel Length Position ( z/L ). Fig. 2.25 Constant electrostatic potential contours based on the analytical solution (solid curves) for DMG MESFETs, compared with ISE simulation results (dash curve). Here, V ds = 1V, L=500 nm, and L 1 : L 2 = 1 : 1.. 44. 1.

(58) 2.9 Threshold Voltage Roll-off Model Threshold voltage is a very important parameter in circuit design. A general definition for the threshold voltage of SOI MESFETs is an abrupt transition between the turn-on and turn-off condition [9] [28]. In SOI MESFETs, the threshold voltage is defined as the gate voltage which causes the minimum bottom potential to become zero. However, the exact solution form of the threshold voltage is too complex to be used in analyzing the subthreshold characteristics. To obtain the simple and feasible analytical threshold voltage model, all parameters are linearlized in a linear equation related to V gs [29]. Therefore, the threshold voltage for the DMG SOI MESFETs is obtained as qN d  tsi 2  a1  tsi  b1  2 PQ 1 1 sin  k n 1t si   2 T11U11 sin  k m 1 xmin  sin  k n 1t si   0 2 si (2.94) where a1  a1'  Vgs  a1". (2.95). b1  Vgs   bi1. (2.96). P1  P1'  Vgs  P1". (2.97). Q1  Q1'  Vgs  Q1". (2.98).  E ' e k11L1 T11   A11'  11 2 .   " E11" ek11L1     Vgs   A11  2   . (2.99).  E ' e  k11L1 U11   B11'  11 2 .   " E11" e  k11L1     Vgs   B11  2   . (2.100). with P  ' 1. . . C1'  e kn1W  1. 2Sinh  kn 1W . 45. (2. 101).

(59) P  " 1. Q  ' 1. . . . C1'  e  kn1W  1. 2Sinh  kn 1W . Q . a1" . (2.102). 2Sinh  kn 1W . " 1. a1' . . C1"  e kn1W  1. . (2.103). . C1"  e  kn1W  1. 2Sinh  kn 1W .  ox  tsi   ox   si  tox . 2   bi1  Vbs  V fb   ox   si +q  N d  tsi  tsi   ox  2  tox   si  2   si  tsi   ox   si  tox . C1' . (2.104). (2.105). (2.106). b1'  1. (2.107). b1"   bi1. (2.108). a1'    b1' . (2.109). . qN d    a1"    Vbi  b1"   2 si. (2.110). A . e k11  L1  L2   F1'  E11' C osh  k11 L1    G1'. (2.111). A . e k11  L1  L2   F1"  E11" C osh  k11 L1    G1". (2.112). B . e  k11  L1  L2   F1'  E11' C osh  k11 L1    G1'. (2.113). B . e  k11  L1  L2   F1"  E11" C osh  k11 L1    G1". (2.114). C1" . ' 11. " 11. ' 11. " 11. . 2Sinh  k11  L1  L2  . 2Sinh  k11  L1  L2  . 2Sinh  k11  L1  L2  . 2Sinh  k11  L1  L2  . 46.

(60) Where F1' , E11' , etc. in above equations are defined as 2  2  1'   km 11'  E11'  . (2.115). E11" . (2.116). F1'  F1"  G1'  G1" .  " 2  2  1   km 11" .  ' 2  2   2   km 1 2' . (2.117).  " 2  2   2   km 1 2" . (2.118).  ' 2  2   3   km 1 3' . (2.119).  " 2  2   3   km 1 3" . (2.120). . 1'   a2'  a1'      b2'  b1'   . (2.121). 1"   a2"  a1"      b2"  b1"   . (2.122).  2'   a1'    b1'  . (2.123).  qN d     a1"    Vbi  b1"     2 si .  2"  . (2.124). 3'   a2'    b2'  . (2.125).  qN d     a2"    Vbi  Vds  b2"     2 si .  3"  . (2.126). . . km 1  R1'  S1'  P1'  Q1'    1  R1'  P1'   e  kn1W   S1'  Q1'   e kn1W    1'  k112. . (2.127). . km 1  R1"  S1"  P1"  Q1"    1  R1"  P1"   e  kn1W   S1"  Q1"   e kn1W    (2.128)   2 k11 " 1. . . km 1  P1'  Q1'    1 P1'  e  kn1W  Q1'  e kn1W    k112 ' 2. 47. (2.129).

(61) . . . . . . km 1  P1"  Q1"    1 P1"  e  kn1W  Q1"  e kn1W    k112 " 2. km 1  R1'  S1'    1 R1'  e  kn1W  S1'  e kn1W    k112 ' 3. km 1  R1"  S1"    1 R1"  e  kn1W  S1"  e kn1W    k112 " 3. If the drain voltage is small,. P1' Q1'  P1" Q1". (2.130). (2.131). (2.132). is tenable and let G  P1'Q1' ,. H  P1"Q1" , then eq. (2.94) can be rewritten as  qN d  tsi 2  a1  tsi  b1  2  GVgs  H  sin  kn 1tsi   2 T11U11 sin  km 1 xmin  sin  kn 1tsi   0 2 si. (2.133) From eq. (2.133), eq. (2.99), and eq. (2.100), one can obtain the following equations.  qN d  2  2  tsi  a1  tsi  b1  2  GVgs  H  sin  kn 1tsi    T11U11   si 2sin  km 1 xmin  sin  kn 1tsi        T11U11  T11' U11' Vgs2  T11"U11'  T11' U11"  Vgs  T11"U11". 2. (2.134). (2.135). Threshold voltage model can be simplified as simple linear equation with one variable V gs . Let eq. (2.134) be equal to eq. (2.135), we obtain the threshold voltage V t,S .. T U " 11. ' 11.  T11' U11"  2 I1 I 2  .  2I I. 1 2.  T11"U11'  T11' U11"   4   I12  T11' U11'    I 22  T11"U11"  2. 2   I12  T11' U11' . (2.136). 48.

(62) Where I 1 and I 2 in above equations are defined as 2G sin  kn 1tsi   a1' tsi  b1' I1  2sin  km 1 xmin  sin  kn 1tsi . qN d  tsi 2  a1"  tsi  b1"  2 H sin  kn 1tsi  2 I 2  si 2sin  km 1 xmin  sin  kn 1tsi . (2.137). (2.138). For the sufficient channel length of L>300 nm, U11' and U11" in eq. (2.138) are approaching to zero, which results in V t,L and ΔV t,S as Vt , L  . Vt , S.  2 I 2T11' U11'  I1  T11"U11'  T11' U11"    . I2 I1. (2.139). 2   T11"U11'  T11' U11"   4   I12  T11' U11'    I 22  T11"U11"    2 I1  I12  T11' U11' .  2I I. 1 2. (2.140) Where V t,L is the threshold voltage for the long-channel devices, and ΔV t,S is the threshold voltage roll-off caused by the short channel effects. The threshold voltage roll-off (V t,S ) predicted by the analytical solution is in good agreement with those from numerical simulation. Fig. 2.26 shows the dependence of threshold voltage roll-off on the channel length for the different ratio of L 1 and L 2 . It is seen that as the ratio value of L 1 is higher than L 2 , the threshold voltage roll-off is reduced more slowly. Fig. 2.27 shows the dependence of voltage roll-off on the channel length for different work function of M 2 . It is seen that as the work function of metal 2 increased, the threshold voltage roll-off is reduced more slowly. Fig. 2.28 shows the threshold voltage roll-off versus the channel length for different silicon thicknesses. The plot indicates that the threshold voltage roll-off increases rapidly when the channel length decreases, particularly for the silicon thickness increased to 60 nm. This is because the gate gradually loses control of the channel as the silicon steadily increases to 60. 49.

(63) nm. Fig. 2.29 shows the effect of the silicon film width on the roll-off of the threshold voltage of the devices, and the 2-D models can not predict the threshold voltage accurately. It is seen that a larger channel width will cause more threshold voltage roll-off, especially for the smaller channel length [30-31].. 50.

(64) Threshold Voltage Roll-off , Vt,s (V). 0. -0.2. tox = 300 nm Symbol : ISE W = 150 nm Solid line : Model tsi = 40 nm Vds = 0.5 V Nd = 1017 cm-3  L1 : L2 = 1:4  L1 : L2 = 1:1 M1= 5.04 eV : L L  1 2 = 4:1 M2= 4.54 eV. -0.4. 100. 150. 200. 250. 300. 350. 400. Channel Length , L (nm) Fig. 2.26 The dependence of threshold voltage roll-off on the channel length for the. Threshold Voltage Roll-off , Vt,s (V). different ratios of L 1 and L 2 .. 0. -0.1 tox = 300 nm W = 150 nm Symbol : ISE t = 40 nm Solid line : Model si Vds = 0.5 V     Nd = 1017 cm-3   M1= 5.04 eV   L1 : L2 = 1:1. -0.2. -0.3. -0.4 100. 150. 200. 250. 300. 350. Channel Length , L (nm) Fig. 2.27 The dependence of threshold voltage roll-off on the channel length for the different work functions of M 2 .. 51.

(65) Threshold Voltage Roll-off , Vt,s (V). 0 -0.25 -0.5. tox = 300 nm W = 150 nm Symbol : ISE Solid line : Model Vds = 0.5 V Nd = 1017 cm-3  tsi = 20 nm M1= 5.04 eV. -0.75.  tsi = 40 nm  tsi = 60 nm. -1 100. 150 200 250 Channel Length , L (nm). M2= 4.54 eV L1 = L2. 300. 350. Fig. 2.28 The dependence of threshold voltage roll-off on the channel length for the. Threshold Voltage Roll-off , Vt,s (V). different silicon film thicknesses.. 0. -0.2 tox = 300 nm tsi = 40 nm Symbol : ISE Solid line : Model Vds = 0.5 V Nd = 1017 cm-3  W = 100 nm M1= 5.04 eV. -0.4.  W = 150 nm  W = 200 nm. M2= 4.54 eV L1 = L2. -0.6 100. 150. 200. 250. 300. 350. Channel Length , L (nm) Fig. 2.29 The dependence of threshold voltage roll-off on the channel length for the different silicon film widths.. 52.