4.1 Conclusions
Based on the exact solution of the 2-D and 3-D Poisson equation, a new analytical compact model has been successfully developed. The 2-D analytical model for the SOI G4-FET have well predicted the coupling effects of threshold voltage related to the front gate with all possible biasing conditions of the lateral gates and the back gate. To more precisely demonstrate the analytical model, the 3-D model of the SOI G4-FET is developed for the short-channel behavior of SOI G4-FET with different device parameter. To decrease the threshold voltage roll-off, we could choose a thin silicon film, a narrow channel width, and use thinner front gate oxide to avoid SCEs for the SOI G4-FET. In addition, the reverse bias of junction gate causes the deplete region more invaded at lateral silicon film and make more degradation of threshold voltage related to the channel length.
4.2 Future Works
As for the future work, the following researching tasks are suggested:
1. The present study can be well expended to 3-D modeling of subthreshold swing and subthreshold current, and drain-current model for SOI G4-FET operated at DAA mode.
2. The present study can also be applied to the SOI G4-FET with localized interface trapped charges.
References
1. Blalock, B.J., et al., The multiple-gate MOS-JFET transistor, in Int. J. High Speed Electron. Syst. 2002. pp. 511-520.
2. Dufrene, B., et al., Investigation of the four-gate action in G(4)-FETs. Ieee Transactions on Electron Devices, 2004. 51(11): pp. 1931-1935.
3. Akarvardar, K., et al. Evidence for reduction of noise and radiation effects in G4-FET depletion-all-around operation. in Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European. 2005.
4. Akarvardar, K., et al., Low-frequency noise in SOI four-gate transistors, in Ieee Transactions on Electron Devices. 2006. pp. 829-835.
5. Akarvardar, K., et al., Total-dose radiation hardness of the SOI 4-gate transistor (G4-FET). in proc. ECS SOI Conf., 2005. 2005-3: pp. 99-106.
6. Terry, S.C., et al. Temperature-compensated reference circuits for SOI. in SOI Conference, 2004. Proceedings. 2004 IEEE International. 2004.
7. Akarvardar, K., et al. A novel four-quadrant analog multiplier using SOI four-gate transistors (G4-FETs). in Solid-State Circuits Conference, 2005.
ESSCIRC 2005. Proceedings of the 31st European. 2005.
8. Fijany, A., et al., The G4-FET: A universal and programmable logic gate. in proc.
31th ESSCIRC, 2005: pp. 499-502.
9. Akarvardar, K., et al. Four-Gate Transistor Voltage-Controlled Negative Differential Resistance Device and Related Circuit Applications. in International SOI Conference, 2006 IEEE. 2006.
10. Takagi, H. and G. Kano, Complementary JFET negative-resistance devices.
Solid-State Circuits, IEEE Journal of, 1975. 10(6): pp. 509-515.
11. Cristoloveanu, S., K. Akarvardar, and P. Gentil. A review of the SOI four-gate transistor. in Solid-State and Integrated Circuit Technology, 2006. ICSICT '06.
8th International Conference on. 2006.
12. Akarvardar, K., S. Cristoloveanu, and P. Gentil, Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor. Ieee Transactions on Electron Devices, 2006. 53(10): pp.
2569-2577.
13. Chiang, T.K., New Analytical Model for Short-Channel Fully Depleted Dual-Material Gate Silicon-on-Insulator Metal Semiconductor Field-Effect Transistor. Japanese Journal of Applied Physics, 2008. 47(12): pp. 8743-8748.
14. DECVISE, Three-dimensional device simulation program. ISE, 2003.
15. Akarvardar, K., et al., Depletion-all-around operation of the SOI four-gate transistor. Ieee Transactions on Electron Devices, 2007. 54(2): pp. 323-331.
16. Akarvardar, K., et al. Multi-bias dependence of threshold voltage, subthreshold swing, and mobility in G4-FETs. in European Solid-State Device Research, 2003.
ESSDERC '03. 33rd Conference on. 2003.
17. Akarvardar, K., et al. Surface vs. bulk noise in SOI four-gate transistors. in SOI Conference, 2005. Proceedings. 2005 IEEE International. 2005.
18. Jones, B.K. and G.P. Taylor, Spectroscopy of surface states using the excess noise in a buried-channel MOS transistor. Solid-State Electronics, 1992. 35(9):
pp. 1285-1289.
19. Watanabe, T., Low-noise operation in buried-channel MOSFET's. Electron Device Letters, IEEE, 1985. 6(7): pp. 317-319.
20. Wilcox, R.A., J. Chang, and C.R. Viswanathan, Low-temperature characterization of buried-channel NMOST. Electron Devices, IEEE Transactions on, 1989. 36(8): pp. 1440-1447.
21. Reddy, G.V. and M.J. Kumar, A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation.
Nanotechnology, IEEE Transactions on, 2005. 4(2): pp. 260-268.
22. Joachim, H.O., et al., Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 μm gate length. Electron Devices, IEEE Transactions on, 1993. 40(10): pp. 1812-1817.
23. Xiaoping, L. and T. Yuan, A 2-D analytical solution for SCEs in DG MOSFETs.
Electron Devices, IEEE Transactions on, 2004. 51(9): pp. 1385-1391.
24. Chiang, T.K., A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET's. Microelectronics Reliability, 2009. 49(2): pp. 113-119.
25. Agrawal, B., V.K. De, and J.D. Meindl, Three-dimensional analytical subthreshold models for bulk MOSFETs. Electron Devices, IEEE Transactions on, 1995. 42(12): pp. 2170-2180.
26. Pilja, D.Z., et al. An analytical 3-D model for small dimensions MOSFETs' threshold voltage. in Microelectronics, 2000. Proceedings. 2000 22nd International Conference on. 2000.
27. Mutlu, A.A. and M. Rahman. Two-dimensional analytical model for drain induced barrier lowering (DIBL) in short channel MOSFETs. in Southeastcon 2000. Proceedings of the IEEE. 2000.
28. Chamberlain, S.G. and S. Ramanan, Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations. Electron Devices, IEEE Transactions on, 1986. 33(11): pp. 1745-1753.
29. Adan, A.O., K. Higashi, and Y. Fukushima, Analytical threshold voltage model for ultrathin SOI MOSFETs including short-channel and floating-body effects.
Electron Devices, IEEE Transactions on, 1999. 46(4): pp. 729-737.
30. Omura, Y., A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator. Electron Devices, IEEE Transactions on, 1982.
29(11): pp. 1749-1755.
31. Pandey, P., B.B. Pal, and S. Jit, A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFETs.
Electron Devices, IEEE Transactions on, 2004. 51(2): pp. 246-254.
32. Guo, J.Y. and C.Y. Wu, A new 2-D analytic threshold-voltage model for fully depleted short-channel SOI MOSFET's. Electron Devices, IEEE Transactions on, 1993. 40(9): pp. 1653-1661.