4.5 Experimental Results
4.5.2 Chip Measurement
The S21 testing setup of channel is depicted in Fig. 4.32. It utilizes the network analyzer, Agilent E8364B PNA, to measure S21. We use the testing results to help us knowing the profile of channels, and then, design the gain-boost of equalizer.
56
Fig. 4.33. Time-domain testing setup of chip, including channels and cables.
When we measure the eye-diagram of chip with time-domain instruments, the testing environmental loss can’t be neglected anymore, especially as the data rate increasing up to tens Gb/s. The time-domain testing setup of chip is depicted in Fig. 4.33. The data pattern is generated by pattern generator, Agilent N4901B serial BERT. In this work, the chip is demonstrated with 13.5Gb/s data rate and PRBS7 data pattern. According to Fig.
4.33, these external losses are resulted from signal traces on PCB and Cables. Fig. 4.34 shows the signal traces on PCB, which the length are totally about 2-inch of length from input-end to output-end. Hence, we would measure such loss to know how much external loss from signal traces, and the test kit is shown in Fig. 4.35. Furthermore, we set the 2-inch as our shortest channel length in COB testing assembly. Fig. 4.36 and Fig.
4.37 show the measured S21 of channels and cable (60cm). The maximum channel loss
57
Fig. 4.34. PCB layout view.
Fig. 4.35. Test kit of PCB trace, about 2-inch of length.
of the longest channel, 20-inch, is 19.3dB at 6.75GHz. The 2-inch has about 3dB loss at 6.75GHz. The cable results in 0.6dB of external loss at 6.75GHz. Thus, the overall loss that the equalizer need to compensate is 20.5dB at 6.75GHz.
2-inch
58
3 6 9 12 15
-50 -40 -30 -20 -10 0
Magnitude(dB)
Frequency(GHz)
2-inch 20-inch
Fig. 4.36. Measured S21 of channels.
3 6 9 12 15
-1.2 -0.9 -0.6 -0.3 0.0
Magnitude(dB)
Frequency(GHz) Fig. 4.37. Measured S21 of cable.
59
2 4 6 8 10
-15 -12 -9 -6 -3 0
Magnitude(dB)
Frequency(GHz)
Vctrl=0V Vctrl=0.4V Vctrl=0.8V
Fig. 4.38. Measured S21 of overall chip.
Fig. 4.38 depicts the measured S21 of overall chip. The maximum peaking is about 12dB. Fig. 4.39 shows the measured eye-diagrams which are before equalization with different channel lengths, 20-inch and 2-inch. We see the eye-diagram of 20-inch before equalization is closed. Fig. 4.40, Fig. 4.41, Fig. 4.42 and Fig. 4.43 show the measured eye-diagrams which are after equalization under different input swings and different channel lengths, 20-inch, 8-inch and 2-inch.
60
(a)
(b)
(c)
Fig. 4.39. Measured eye-diagrams which is before equalization with 400mV input swing and (a) 20-inch (b) 14-inch (c) 2-inch
61
(a)
(b)
(c)
Fig. 4.40. Measured eye-diagrams which is after equalization with 300mV input swing and (a) 20-inch (b) 14-inch (c) 2-inch
62
(a)
(b)
(c)
Fig. 4.41. Measured eye-diagrams which is after equalization with 400mV input swing and (a) 20-inch (b) 14-inch (c) 2-inch
63
(a)
(b)
(c)
Fig. 4.42. Measured eye-diagrams which is after equalization with 500mV input swing and (a) 20-inch (b) 14-inch (c) 2-inch
64
(a)
(b)
(c)
Fig. 4.43. Measured eye-diagrams which is after equalization with 600mV input swing and (a) 20-inch (b) 14-inch (c) 2-inch
65
Fig. 4.44. The jitter comparison.
300 400 500 600
Fig. 4.45. The Vctrl comparison.
The measured jitter performance is shown in Fig. 4.44. The maximum jitter is less than 0.31UI. Fig. 4.45 depicted Vctrl comparison. Fig. 4.46 shows the measured noise of
66
(a)
(b)
Fig. 4.46. The measured results of chip. (a) utilizing Spectrum analyzer (Agilent E4440A) (b) utilizing oscilloscope (Agilent 86100A)
chip by two testing instruments. The noise are 0.78mVrms and 0.76mVrms, and the simulated noise is about 0.8mVrms. According to eq. (2.2), as long as the output swingp-p is larger than 12.6mV, the BER could be smaller than 10-12. Fig. 4.47 depicted BER results, and the input swing can be decreased to 80mVp-p which the BER still smaller than 10-12. Table 4.1 shows the overall performance comparison of this work.
67
100 200 300 400 500 600 10-13
10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2
Bit error rate
Input swingp-p(mV)
Fig. 4.47. The BER results with different input swingp-p.
68
Table 4.1 Performance Comparison with Previous Papers.
JSSC’10
* without adaptive schematics’ power
**only active schematics Power FoM DataRate Loss
69
Chapter 5
Conclusion and Future Work
This thesis proposes a positive-feedback based equalizer using slope detector. With the help of slope detector, we avoid the requirement of using offset-sensitive rectifiers. And the adaptive equalizer tolerates large input dynamic range, or called large input swing.
Since the equalizer dominates the power consumption, we utilize the positive-feedback based equalizer to save power consumption. Furthermore, in the recently published papers, the compensating channel loss is about 20dB at Nyquist rate. The channel loss may can be compensated up to 30dB.
70
Appendix A
A 6Gb/s Adapative Equalizer with Large Input Dynamic Range Using Offset-Insensitive Slope Detector
This appendix presents a 6Gb/s adaptive eequalizer using the slope deteector. The adaptive equalizer is capable of compensating the channel loss of 22dB at Nyquist rate by 0.18μm CMOS technology.
Fig. B.1 depicts the architecture of the proposed 6Gb/s adaptive equalizer with slope detector. The detection schematics include swing detector, common-mode detector (CM detector), reference generator, and slope detector. Fig. B.2 shows the relations between Vi, VSWD, VCM, Vref1 and Vref2. The swing detector and CM detector can detect the swing voltage level (VSW) and common-mode voltage level (VCM) of signal, Vi. And the Vref1 and Vref2 can be generated by reference generator according to the voltage level of VSWD and VCM.
71
Fig. B.1. The architecture of adaptive equalizer with slope detector.
Vi
Fig. B.3. Block diagram of Equalizer.
The proposed block diagrams of equalizer is depicted in Fig. B.3. The equalizer’s gain-boost is tuned by interpolation weighting controller (IWC) between peaking path and all-pass path. Furthermore, we say the peaking tuning is control by the coefficient of α. the range of α is between 0 and 1. The peaking path provides the fixed peaking response which is combined with three peaking stages, EQH1, EQH2 and EQH3.
72
Fig. B.4. The schematic of EQH2 with RC degeneration technique.
Vi
Fig. B.5. The schematic of EQH1 and EQH3 with RC degeneration and negative capacitive techniques.
And the all-pass path provides the wide and flatness response. For group-delay consideration, the all-pass path utilizes one wide-bandwidth stage, EQL1, to overcome the disparate group-delay through two parallel paths of equalizer. Fig. B.4 and Fig. B.5 depict the schematics of peaking path. The EQH2 use RC degeneration technique, and EQH1 and EQH3 use the RC degeneration and negative capacitance techniques. Fig. B.6 depicts the schematic of all-pass path. It only utilizes source degeneration technique.
The interpolation weighting controller (IWC) is designed for
73 Vi
RD RD
M1 M2 Vo
RS
Cp Cp
Fig. B.6. The schematic of EQL1 with source degeneration technique.
Vref_iwc Vctrl
RD RD
Vo
Cp Cp
Vi1 Vi2
CS
Itail
It1 It2
Ib1 Ib2
Fig. B.7. The schematic of interpolation weighting controller (IWC).
controlling the parameter of α which can tune the gain-boost of equalizer, as shown in Fig. B.7. Fig. B.8 shows the magnitude response of equalizer under Vctrl varying from 0.4V to 1.2V. The maximum gain-boost is about 18dB at 3GHz when Vctrl=1.2V.
74
Fig. B.8. Simulated frequency response of equalizer with different voltage of Vctrl.
Vi M1 M2
Fig. B.9. The schematic of swing detector.
V
iV
SWFig. B.10. The transient response of swing detector.
The proposed schematic of swing detector is depicted in Fig. B.9, it’s improved from previous paper [25-26] which is called peak detect and hold (PDH) schematic.
And Fig. B.10 shows the transient response of swing detector. VSW is almost the same to the swing voltage of signal, almost obtains the correct value of swing.
75 R
C VCM R
Vi+ V
i-Fig. B.11. The schematic of common-mode detector.
VCM
Fig. B.12. The schematic of reference generator.
C
Fig. B.13. The schematic of operation-amplifier in CMFB path.
The schematic of common-mode detector is depicted in Fig. B.11. It utilizes the differential signal, Vi+ and Vi-, to cancel input feed-through from each other. And then, only keeps the DC information of signal.
As the mentioned in Fig. B.2, we utilize VSW and VCM to generate Vref1 and Vref2. Fig. B.12 depicts the proposed reference generator to accomplish this requirement.
The transfer function is derived as :
76
B.15 depicts the transient response of the average current of I1-I2 (Iavg,) in slope detector when the input signal is ideal PRBS7.
Vi+
Fig. B.14. The schematic of slope detector, current mirror and integrator.
77
Fig. B.15. The transient response of slope detector.
Fig. B.16. Die photograph.
Fig. B.16 is the die photograph of the chip.
Fig B.17 shows the measured S21 of channels. The maximum channel loss of the longest channel, 61-inch, is 23.3dB at 3GHz. Fig. B.18 shows the measured eye-diagrams which are before equalization with different channel lengths, , 61-inch , 28-inch 12-inch and 0-inch. We see the eye-diagram of 61-inch before equalization is closed. Fig. B.19, Fig B.20, Fig. B.21 and Fig. B.22 show the measured eye-diagrams which are after equalization under different input swing and different channel length.
78
1 2 3 4 5 6
-50 -40 -30 -20 -10 0
Magnitude(dB)
Frequency(GHz)
12-inch 28-inch 61-inch
Fig. B.17. Measured S21 of channels.
(a) (b)
(c) (d)
Fig. B.18. Measured eye-diagrams which is before equalization under 400mV input swing with (a) 61-inch (b) 28-inch (c) 12-inch (d) 0-inch
79
(a) (b)
(c) (d)
Fig. B.19. Measured eye-diagrams which is after equalization under 300mV input swing with (a) 61-inch (b) 28-inch (c) 12-inch (d) 0-inch
(a) (b)
80
(c) (d)
Fig. B.20. Measured eye-diagrams after equalization when input swing is 400mVp-p under (a) 61-inch (b) 28-inch (c) 12-inch (d) 0-inch
(a) (b)
(c) (d)
Fig. B.21. Measured eye-diagrams after equalization when input swing is 500mVp-p
under (a) 61-inch (b) 28-inch (c) 12-inch (d) 0-inch
81
(a) (b)
(c) (d)
Fig. B.22. Measured eye-diagrams after equalization when input swing is 600mVp-p
under (a) 61-inch (b) 28-inch (c) 12-inch (d) 0-inch
82
Table B.1 shows the performance comparison of this work. This chip demonstrates well adaptive equalization at 6Gb/s data rate for trace lengths up to 61 inches in 0.18μm CMOS technology while consuming only 27mW (without output buffer) from a 1.8V power supply.
Table B.1 Performance Comparison
JSSC’03 [2] JSSC’04 [3] TCAS-II’10 [28] This work Technology 0.13μm CMOS 0.18μm CMOS 0.18μm CMOS 0.18μm CMOS
Supply Voltage (V) 1.5 1.8 1.6 1.8
Data rate (Gb/s) 5 3.5 5 6
Channel Loss (dB) 18* 16 14 23.3
Jitterp-p (UI) 0.39 0.39 0.28 0.25
Input Swingp-p (V) N.A. 0.6~1.4 0.75 0.2~0.6
Power(mW) 10* 80 17.6 27
Area (mm2) 0.1* 0.35** 0.1** 0.09**
FoM 0.11 1.43 0.25 0.19
* Only equalizer **Only active schematics Power
FoM DataRate Loss
83
References
[1] H. Higashi, et al., "A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization," IEEE Journal Solid-State Circuits,, vol. 40, pp. 978-985, 2005.
[2] Y. Kudoh, et al., "A 0.13um CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer," IEEE Journal Solid-State Circuits,, vol. 38, pp. 741-746, 2003.
[3] J.-S. Choi, et al., "A 0.18um CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method," IEEE Journal Solid-State Circuits,, vol. 39, pp. 419-425, 2004.
[4] J. Lee, "A 20Gb/s Adaptive Equalizer in 0.13um CMOS Technology," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2006, pp. 273-282.
[5] S. Gondi, et al., "A 10Gb/s CMOS adaptive equalizer for backplane applications," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2005, pp. 328-601 Vol. 1.
[6] J. H. Lu, et al., "A passive filter for 10-Gb/s analog equalizer in 0.18-um CMOS technology," in Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian, 2007, pp. 404-407.
[7] D. H. Shin, et al., "A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS," in IEEE Custom Integrated Circuits Conference,, 2009, pp.
117-120.
[8] J.-H. Lu, et al., "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology," IEEE Transactions on Circuits and Systems II: Express Briefs,, vol. 56, pp. 97-101, 2009.
[9] J.-H. Lu, et al., "A 40Gb/s low-power analog equalizer in 0.13um CMOS technology," in IEEE Symposium on VLSI Circuits,, 2008, pp. 54-55.
[10] H. Wang and J. Lee, "A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology," IEEE Journal Solid-State Circuits,, vol.
45, pp. 909-920, 2010.
[11] S. A. Ibrahim and B. Razavi, "A 20Gb/s 40mW equalizer in 90nm CMOS technology," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2010, pp. 170-171.
[12] Y.-C. Huang and S.-I. Liu, "A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2011, pp. 356-358.
84
[13] Y.-M. Ying and S.-I. Liu, "A 20Gb/s digitally adaptive equalizer/DFE with blind sampling," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2011, pp. 444-446.
[14] B. Razavi, Design of Integrated Circuits for Optical Communications, First ed.
New York: McGRAW-Hill, 2003.
[15] J. G. Proakis and M. Salehi, Digital Communications, Fifth ed. New York:
McGRAW-Hill, 2008.
[16] S. Gondi and B. Razavi, "Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers," IEEE Journal Solid-State Circuits,, vol. 42, pp. 1999-2011, 2007.
[17] G. Zhang, et al., "A BiCMOS 10Gb/s adaptive cable equalizer," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2004, pp. 482-541 Vol.1.
[18] H. Uchiki, et al., "A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2008, pp. 104-599.
[19] B.-W. Yi, "A 3.125-Gb/s Optical Receiver with Adaptive Equalizer in 0.13um Technology," Master, Electronic Engineering, National Chiao Tung University, Hsinchu, Taiwan, 2009.
[20] C.-C. Yang, "A10-Gb/s Adaptive Equalizer with Wide Input Swing Range in 0.13um CMOS Technology," Master, Electronic Engineering, National Chiao Tung University, Hsinchu, Taiwan, 2011.
[21] X. Li, et al., "Gm-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-μm CMOS," IEEE Journal Solid-State Circuits,, vol. 40, pp. 2609-2619, 2005.
[22] W. Zhuo, et al., "Using capacitive cross-coupling technique in RF low noise amplifiers and down-conversion mixer design," in Proceedings of the 26rd European Solid-State Circuits Conference,, 2000, pp. 77-80.
[23] R. Schaumann and M. E. V. Valkenburg, Eds., Design of Analog Filters. New York: Oxford, 2001, p.^pp. Pages.
[24] H.-C. Nee, "A 6Gb/s Adaptive Equalizer With Overshoot Detection in 0.18um CMOS Technology," Master, Electronic Engineering, National Chiao Tung University, Hsinchu, Taiwan, 2011.
[25] M. N. Ericson, et al., "A low-power, CMOS peak detect and hold circuit for nuclear pulse spectroscopy," Nuclear Science, IEEE Transactions on, vol. 42, pp.
724-728, 1995.
[26] M. W. Kruiskamp and D. M. W. Leenaerts, "A CMOS peak detect sample and hold circuit," Nuclear Science, IEEE Transactions on, vol. 41, pp. 295-298,
85
1994.
[27] C.-M. Tsai, "A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18um CMOS Technology," IEEE Journal Solid-State Circuits,, vol. 44, pp. 2671-2677, 2009.
[28] K.-H. Cheng, et al., "A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications," IEEE Transactions on Circuits and Systems II: Express Briefs,, vol. 57, pp. 324-328, 2010.