Circuit Design and Analysis
3-1 Introduction
In this chapter, the proposed AGC circuit for the application of ASK receiver has been presented, The components in the proposed AGC circuit are based on the fundamentals of the circuits, which have been presented in chapter 3, to improve the performance to meet the required specifications, In this chapter, we will compare the performance of the proposed circuit with the conventional circuits, as presented in chapter 2.
3-2 Design Flow
The design flow chart is depicted in Fig. 3-1. The design flow of used is the full custom design flow.
Specifications
Circuit Design
Simulations
Circuit Layout Satisfy Specifications?
DRC/LVS
Layout Verifications
GDSII
CIC Fabrication
Measurment/Verify
Satisfy Specifications?
Good Job !!
NO
Yes
Yes
Yes
NO
NO NO
Fig. 3-1 Design flow chart
The first step of flow is defined the specification of circuit which include frequency, output level, process technology… etc. The second step of flow is to select the circuit architecture. Simulation and verify the function of circuit by EDA tools is the third step of flow. In this design, ADS of Angilent is selected for simulator. After simulations finished, Cadence Corporation’s CAD tools to establish the circuit layout, design rule check (DRC). One thing need to mention is that the GCTC Corporation didn’t provide layout versus schematic (LVS) file. So LVS have to check by own self. Then Dracula and ADS are used for layout verification and post-layout simulation. The design technology is GCTC HBT process.
3-3 Circuit specifications
Process GCTC HBT 2um Amplitude Wave Carrier 925 MHz Signal 70KHz Ambient Temperature 25°C
Table 1 Parameter of simulation
The process is GCTC HBT 2um. The design is a block of RFID receiver chain. The ASK modulation is the receiving signal. The carrier of ASK modulation signal is 925 MHz for Electronic Product Code (EPC) standard. The signal is 70 kHz. The ambient temperature in simulation is 25°C in table 1. The electric parameter is list in table 2.
Symbols conditions Minimum Typical Maximum Unit
Supply Voltage Vcc 2.97 3.3 3.63 V
Supply Current Icc 16.2 18 19.2 mA
Maximum sensitivity SM VOD=3mV 700 uV
Detector output
Voltage VOD 3mV<Vin<88mV 8 9 10 mV
Range of AGC A 20 dB
Output Voltage
Flatness V 2 dB
Table 2 Summaries of the circuit specifications
The proposed AGC circuit system block diagram is depicted in Fig.
3-2. According to the specifications, the VGA provides the dynamic gain range. The capacitance achieves the loop filter and Peak detector.
Fig. 3-2 The structure of the AGC loop
The V ctr control the
Gain of VGA.
3-4 Input signal
Vin Vin
AM_ModTuned MOD2 Rout=50 Ohm Fnom=10 MHz ModIndex=0.3 AM_ModTuned
MOD1 Rout=50 Ohm Fnom=10 MHz ModIndex=0.3
VtSine SRC9
Phase=0 Damping=0 Delay =0 nsec Freq=70 GHz Amplitude=1 V Vdc=0 V V_1Tone
SRC8 Freq=925 MHz V=polar(100,0) mV V_1Tone
SRC4 Freq=925 MHz
V=polar(100,0) mV R
R19 R=50 Ohm
VtPulse SRC6
Period=14.84 usec Width=7.12 usec Fall=300 nsec Rise=300 nsec Edge=linear Delay=0 nsec Vhigh=1 V Vlow=-1 V
t
R R18 R=50 Ohm
Fig. 3-3 (a)ASK signal of EPC standard (b)Traditional AM signal
In the ADS, it provides the AM modulation tuned to generate ask modulation signal. The ask modulation signal may have problem in hspice. That is the reason why chose ADS to be the simulator for this design. In the Fig. 3-3(a), the output of ASK mod_tured is the ASK modulation signal. The carrier is a frequency domain source. The data signal is a sequence square wave. In the Fig. 3-3(b), it is the traditional Amplitude Modulation (AM) wave.
The carrier is the same as Fig. 3-3(a), but the data signal is a sine wave. The responds of circuit is the same of the EPC standard ASK signal and traditional AM signal. The process of simulation is faster if the ASK source is used liked Fig. 3-3(b). All the source in process of simulation is exactly the same as Fig. 3-3(b).
Fig 3-4 (a) Amplitude Modulation (b) Amplitude Shift Keying
Fig 3-4 (a) is amplitude modulation signal. Both carrier and signal is sinusoidal signal. Fig (b) is Amplitude shift keying signal. The standard of this signal has been notified in RFID regulation. Both Fig 3-4 (a) and Fig (b) are generated by ADS AM modulator and the modulation index is 0.5.
3-5 Exponential character
Before go to the circuit level. There is an important point had to notice and that would be exponential character. In an automatic gain control loop, to maintain its settling time independent of the input signal levels and a large dynamic control range, an exponential gain control characteristic is required.
However, in CMOS technology, it is difficult to realize the exponential or logarithmic function because of it inherent square or liner characteristics. Although the transistor operating in sub-threshold region has exponential characteristic, it is generally not preferred due to other unfavorable effects, such as noise and bandwidth. Thus, some of the
function.
The approximation errors of pseudo- exponential function to the ideal one is 5%. Alternatively, the Taylor’s series can be utilized to approximate the exponential function.
The approximation error of second-order approximation can be less than 5%. The each bipolar transistor in HBT process has own exponential function without any extra circuit to implement. From chapter 2, VGA is the kernel on determining the system performance in an AGC system.
According to equation (43), a VGA with exponential gain control characteristics is preferred for its large dynamic control range and constant loop settling time independent of the absolute gain.
It is easy to achieve exponential gain characteristics by using bipolar transistors. Because collector current characteristics of bipolar transistor is
V BE Vt
Ise Ic =
The voltage across base and emitter, V
BE
, can generate an exponential characteristic current in collector. Therefore, if exponential gain control is mandatory, parasitic bipolar device is the only solution due to the lack of intrinsic logarithmic characteristics of MOS device when it operates in strong inversion.3-6 Circuit Analysis
Pre-simulation
Fig. 3-5 AGC Circuit
In this design, the source signal is Amplitude Modulation (AM) signal which mentioned in previous section. The AM signal is a Double Side Band (DSB) signal. The DSB signal contains the carrier and sideband components which, when multiplied together, generate frequencies that include the original information signal. Capacitor C1 is a dc block capacitor and coupling capacitor. The AM modulation signal pass through C1. Transistor Q1 is common emitter amplifier. Q2 is a current source. There are few reasons for this combination. Here, the collector is connected to the positive supply and thus is at signal ground.
The input signal is applied to the base, and the output is taken from the
emitter.
The main purpose of the common collector circuit is to connect a source having a large input resistance to a load with a relatively low resistance. Since only a small fraction of the input signal appears between base and emitter, the emitter follower exhibits linear operation for a large range of input-signal amplitude. There is, however, an absolute upper limit imposed on the value of the output- signal amplitude by transistor cutoff. The output signal at the emitter is coupled via a large coupling capacitor C2 to next stage, C2 is dc block capacitor and a coupling capacitor as well.
The purpose of transistor Q3 and Q5 is to maintain the bias of transistor Q2, Q4 and Q6. The negative feedback magnitude will pull down or pull high the transistor bias. In this reason, fixed the bias point is necessary. So that transistor Q3 and Q5 is design for maintain the bias.
Basically transistor Q4, Q6 and Q7 are Variable Gain Amplifiers to amplify the modulation signal. Transistor Q4 and Q6 are common emitter connection to have a high output resistance and to provide substantial voltage and current gains and moderate value input resistance. The amplification is determinate by feedback magnitude.
Transistor Q7 is an amplifier between class AB and class B. The signals will recovery by transistor Q7 and a low pass filter. Resistor R
AGC
and capacitor C4 is a low pass filter to selects the information signal.After the transistor Q7, the signal is then applied across capacitor C4.
Capacitor C4 have to large enough to ignore the rapid frequencies of the carrier but small enough to follow the voltage fluctuations of the waveform envelope.
3-7 Simulation Result
Fig. 3-6 Load line of transistor Q1
Fig. 3-6 Load line of transistor Q2 (con)
Fig. 3-6 Load line of transistor Q3 (con)
Fig. 3-6 Load line of transistor Q4 (con)
Fig. 3-6 Load line of transistor Q5 (con)
Fig. 3-6 Load line of transistor Q6 (con)
The load lines will adoptions with input signal. The input signal is Amplitude Modulation signal with 10 mV. The modulation index is 0.5.
There is an obvious feature in every load line curve and that is the load line cures will convergence into a fixed region because of negative feedback. The load line of transistor Q6 Fig. 3-6 shows this feature obviously.
The load line shows that transistor Q3 and Q5 are high impedance.
Transistor Q3 and Q5 maintains the load line stay in saturation region and won’t convergence to zero. The maximum sensitivity of this AGC circuit is 0.7 mV and list in specification.
The follow simulation result is every node of the circuit transient simulation
1. Minimum input signal 0.7mV Amplitude Modulation signal. The
modulation index is 0.5. The carrier frequency is 925 MHz, signal is 70K Hz.Fig. 3-7 Transient Analysis with 0.7mV input
Fig. 3-7 Transient Analysis with 0.7mV input (con)
Fig. 3-8 Fourier transform of every node with 0.7mV input
Fig. 3-8 Fourier transform of every node with 0.7mV input (con)
2. Input signal 1.5 mV AM signal. The modulation index is 0.5.
Fig. 3-9 Transient Analysis with 1.5mV input
Fig. 3-9 Transient Analysis with 1.5mV input (con)
3. Input signal 15 mV AM signal. The modulation index is 0.5
Fig. 3-10 Transient Analysis with 15mV input
Fig 3-10 Transient Analysis with 15mV input (con)
4. Input signal (0.7 ~ 37 mV)
Auto Gain Control Performance
-60 -50 -40 -30 -20 -10 0
-70 -60 -50 -40 -30 -20
Vin (dBV)
Vout ( dBV)
Fig. 3-11 Vin (dB) V.S. Vout (dB)
Vout2 Vout1 Vout Vin Gain log Vin log Vout log Gain 2.9019 2.8981 0.0038 0.0007 5.428571 -63.098 -48.4043 14.69371 2.8966 2.8788 0.0178 0.0014 12.71429 -57.0774 -34.9916 22.08584 2.8881 2.8482 0.0399 0.002 19.95 -53.9794 -27.9805 25.99886 2.8863 2.8426 0.0437 0.0021 20.80952 -53.5556 -27.1904 26.36524 2.8844 2.8369 0.0475 0.0022 21.59091 -53.1515 -26.4661 26.68542 2.8824 2.8311 0.0513 0.0023 22.30435 -52.7654 -25.7977 26.96779 2.8803 2.8253 0.055 0.0024 22.91667 -52.3958 -25.1927 27.20303 2.878 2.8194 0.0586 0.0025 23.44 -52.0412 -24.642 27.39915 2.8757 2.8135 0.0622 0.0026 23.92308 -51.7005 -24.1242 27.57634 2.8732 2.8076 0.0656 0.0027 24.2963 -51.3727 -23.6619 27.7108 2.8707 2.8018 0.0689 0.0028 24.60714 -51.0568 -23.2356 27.82122 2.8681 2.7959 0.0722 0.0029 24.89655 -50.752 -22.8293 27.92278 2.8654 2.7856 0.0798 0.003 26.6 -50.4576 -21.9599 28.49763 2.8352 2.7365 0.0987 0.004 24.675 -47.9588 -20.1137 27.84514 2.8027 2.6914 0.1113 0.005 22.26 -46.0206 -19.0701 26.9505 2.7712 2.6548 0.1164 0.006 19.4 -44.437 -18.6809 25.75603 2.742 2.6249 0.1171 0.007 16.72857 -43.098 -18.6289 24.46918 2.7156 2.6 0.1156 0.008 14.45 -41.9382 -18.7408 23.19736 2.6918 2.5805 0.1113 0.009 12.36667 -40.9151 -19.0701 21.84505 2.6706 2.5644 0.1062 0.01 10.62 -40 -19.4775 20.52249 2.6517 2.5516 0.1001 0.011 9.1 -39.1721 -19.9913 19.18083
Table 3 Vout and Vin
2.6348 2.5408 0.094 0.012 7.833333 -38.4164 -20.5374 17.87893 2.6198 2.5313 0.0885 0.013 6.807692 -37.7211 -21.0611 16.66 2.6058 2.523 0.0828 0.014 5.914286 -37.0774 -21.6394 15.43805 2.5939 2.5136 0.0803 0.015 5.353333 -36.4782 -21.9057 14.57249 2.5831 2.5026 0.0805 0.016 5.03125 -35.9176 -21.8841 14.03352 2.5739 2.4905 0.0834 0.017 4.905882 -35.391 -21.5767 13.81434 2.5652 2.4789 0.0863 0.018 4.794444 -34.8945 -21.2798 13.61477 2.5575 2.4684 0.0891 0.019 4.689474 -34.4249 -21.0024 13.42248 2.5508 2.4588 0.092 0.02 4.6 -33.9794 -20.7242 13.25516 2.5448 2.4503 0.0945 0.021 4.5 -33.5556 -20.4914 13.06425 2.515 2.417 0.098 0.022 4.454545 -33.1515 -20.1755 12.97607 2.5338 2.4368 0.097 0.023 4.217391 -32.7654 -20.2646 12.50088 2.529 2.4311 0.0979 0.024 4.079167 -32.3958 -20.1843 12.21143 2.5245 2.4263 0.0982 0.025 3.928 -32.0412 -20.1578 11.88343 2.52 2.4211 0.0989 0.026 3.803846 -31.7005 -20.0961 11.60446 2.5148 2.4173 0.0975 0.027 3.611111 -31.3727 -20.2199 11.15282 2.509 2.414 0.095 0.028 3.392857 -31.0568 -20.4455 10.61131 2.5031 2.4109 0.0922 0.029 3.17931 -30.752 -20.7054 10.04666 2.497 2.409 0.088 0.03 2.933333 -30.4576 -21.1103 9.347228 2.4657 2.4 0.0657 0.035 1.877143 -29.1186 -23.6487 5.469947 2.4607 2.3984 0.0623 0.036 1.730556 -28.8739 -24.1102 4.763711 2.456 2.397 0.059 0.037 1.594595 -28.636 -24.583 4.053006
Table 3 Vout and Vin (con)
Fig 3-10 is the cure of different output due to different input and table 3 record the parameter. The dynamic turning range is about 20 dB. The maximum sensitivity is about 0.7 mV when output is 3 mV. The output voltage flatness is about 2 dB.
Post-simulation
(Including Bonding wire and Transmission line effect)
VB2 VC3 VC2
Vin
Vout VC1
VE1 VB1
VB4
VC6 VC5
VC4
VB7 VB5 VB6
V_1Tone SRC4 Fr eq=925 M Hz V=polar ( 1. 5, 0) m V
R R1 R=250 O hm MSABND_MDS
Bend11
M=0. 5 Angle=45 W=25 um Subst =" M Sub1"
M LI N TL13 L=115. 5 um W=25. 0 um Subst =" M Sub1"
MSABND_M DS Bend10
M=0. 5 Angle=45 W=25 um Subst =" M Sub1"
M LI N TL12 L=43. 5 um W=25. 0 um Subst =" MSub1"
Q 8_model Q 2 Q 8_model Q 1
MLI N TL14 L=75 um W=25. 0 um Subst =" M Sub1" M TEE
Tee1
W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"
MTEE Tee2
W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"
M LI N TL15 L=31. 0 um W=25. 0 um Subst =" M Sub1"
R R4 R=500 O hm M SABND_M DS Bend14
M =0. 5 Angle=45 W=25 um Subst =" MSub1"
MLI N TL16 L=172 um W=25. 0 um Subst =" M Sub1"
M SABND_M DS Bend12
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
M LI N TL17 L=134. 5 um W=25. 0 um Subst =" M Sub1"
M LI N TL11 L=70. 72 um W=25. 0 um Subst =" MSub1"
M SABND_M DS Bend9
M =0. 5 Angle=45 W=25 um Subst =" MSub1"
MLI N TL10 L=166. 1 um W=25. 0 um Subst =" M Sub1"
MSABND_M DS Bend8
M=0. 5 Angle=45 W=25 um Subst =" M Sub1"
MLI N TL9 L=120. 82 um W=25. 0 um Subst =" M Sub1"
M SUB M Sub1
Rough=0 um TanD=1. 24 m T=1 um Hu=1. 0e+036 um Cond=1. 0E+50 M ur =1 Er =12. 8 H=100 um MSub
M easEqn M eas3 VBE1=VB1- VE1 VCE1=VC1- VE1 E q n Me a s
M LI N TL22 L=76 um W=25. 0 um Subst =" MSub1"
M LI N TL47 L=262. 3 um W=25. 0 um Subst =" M Sub1"
M TEE Tee9
W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"
M LI N TL20 L=141 um W=25. 0 um Subst =" M Sub1"
Cap_150x150 Cap19
21
R R38 R=50 O hm
AM_M odTuned M O D1 Rout =50 O hm Fnom =10 MHz M odI ndex=0. 3
Vt Sine SRC1
Phase=0 Dam ping=0 Delay=0 nsec Fr eq=70 kHz Amplit ude=1 V Vdc=0 V
R R17 R=18 kO hm
M TEE Tee8
W3=25. 0 um W2=25. 0 um W1=25. 0 um
Subst =" M Sub1" M LI N
TL46 L=94. 3 um W=25. 0 um Subst =" MSub1" M TEE
Tee7
W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"
MLI N TL45 L=56 um W=25. 0 um
Subst =" M Sub1" M TEE
Tee6
W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" MSub1"
M LI N TL44 L=38. 2 um W=25. 0 um Subst =" M Sub1"
M LI N TL29 L=15. 3 um W=25. 0 um Subst =" MSub1"
MSABND_MDS Bend23
M=0. 5 Angle=45 W=25 um Subst =" M Sub1"
MLI N TL43 L=664. 9 um W=15. 0 um Subst =" M Sub1"
M SABND_M DS Bend22
M =0. 5 Angle=45 W=25 um Subst =" MSub1"
M LI N TL42 L=84. 1 um W=25. 0 um Subst =" M Sub1"
Q 10_model Q 9 M LI N TL41 L=47. 51 um W=25. 0 um Subst =" M Sub1"
M TEE Tee5
W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"
R R15 R=295 O hm
M LI N TL40 L=315. 6 um W=15. 0 um Subst =" MSub1"
Q 9_m odel Q 8 M LI N
TL39 L=74 um W=15. 0 um Subst =" M Sub1"
R R14 R=160 O hm M LI N TL37 L=10 um W=25. 0 um Subst =" M Sub1"
MSABND_MDS Bend21
M=0. 5 Angle=45 W=25 um Subst =" M Sub1"
M TEE Tee4
W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"
M LI N TL38 L=106. 5 um W=15. 0 um Subst =" M Sub1"
MLI N TL36 L=22. 5 um W=25. 0 um Subst =" M Sub1"
M CRO SO Cr os1
W4=25. 0 um W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" MSub1"
R R12 R=500 O hm M LI N TL35 L=135. 4 um W=25. 0 um Subst =" M Sub1"
M SABND_M DS Bend20
M =0. 5 Angle=45 W=25 um Subst =" MSub1"MLI N TL34 L=151 um W=15. 0 um Subst =" M Sub1"
M SABND_M DS Bend19
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
M LI N TL33 L=60 um W=25. 0 um Subst =" M Sub1"
Q 8_m odel Q 7
M LI N TL32 L=212. 92 um W=25. 0 um Subst =" M Sub1"
M SABND_M DS Bend18
M =0. 5 Angle=45 W=25 um Subst =" MSub1"
M LI N TL31 L=319. 5 um W=15. 0 um Subst =" M Sub1"
M SABND_M DS Bend17
M =0. 5 Angle=45 W=25 um Subst =" MSub1"
M LI N TL30 L=75. 5 um W=25. 0 um Subst =" M Sub1"
M SABND_M DS Bend16
M =0. 5 Angle=45 W=25 um Subst =" MSub1"
M LI N TL28 L=34. 5 um W=25. 0 um Subst =" M Sub1"
R R13 R=500 O hm M LI N TL27 L=15. 3 um W=25. 0 um Subst =" M Sub1"
Cap_150x150 Cap18
21
M LI N TL26 L=55 um W=25. 0 um Subst =" MSub1"
M LI N TL25 L=15. 3 um W=25. 0 um Subst =" M Sub1"
M LI N TL24 L=168 um W=25. 0 um Subst =" M Sub1"
R R5 R=500 O hm
M SABND_MDS Bend15
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
M LI N TL23 L=70 um W=25. 0 um Subst =" MSub1"
Q 8_m odel Q 3 MLI N
TL21 L=105. 4 um W=25. 0 um Subst =" M Sub1"
M LI N TL19 L=145 um W=25. 0 um Subst =" MSub1"
M LI N TL18 L=105 um W=25. 0 um Subst =" M Sub1"
R R3 R=500 O hm
M SABND_M DS Bend13
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
M SABND_M DS Bend7
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
MLI N TL8 L=201. 1 um W=25. 0 um Subst =" M Sub1"
M SABND_M DS Bend6
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
M LI N TL7 L=52. 4 um W=25. 0 um Subst =" MSub1"
M SABND_M DS Bend5
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
BJT4_NPN BJT1
M ode=nonlinear Tr ise=
Temp=
Region=
Ar ea=
M odel=Q 2P0X9 BJT4_NPN BJT12
M ode=nonlinear Tr ise=
Temp=
Region=
Ar ea=
M odel=Q 2P0X9 MLI N
TL6 L=102. 4 um W=25. 0 um Subst =" M Sub1"
M LI N TL4 L=78. 9 um W=25. 0 um Subst =" M Sub1"
M SABND_M DS Bend3
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
M LI N TL5 L=32. 3 um W=25. 0 um Subst =" MSub1"
MSABND_MDS Bend4
M=0. 5 Angle=45 W=25 um Subst =" M Sub1"
M LI N TL3 L=48. 8 um W=25. 0 um Subst =" MSub1"
M LI N TL2 L=50. 5 um W=25. 0 um Subst =" M Sub1"
Cap_200x200 Cap10
21
M SABND_M DS Bend2
M =0. 5 Angle=45 W=25 um Subst =" MSub1"
MLI N TL1 L=119. 4 um W=25. 0 um Subst =" M Sub1"
M SABND_M DS Bend1
M =0. 5 Angle=45 W=25 um Subst =" M Sub1"
V_DC SRC5
Vdc=3. 3 V C
C6 C=39 nF R
RAG C R=22 O hm
Tran Tran1 MaxTimeStep=1.5 usec StopTime=30 usec StartTime=0.0 nsec
TRANSI ENT
BJT_Model Q 2P0X9
AllPar am s=
Xt i=4 Xt b=- 1 Eg=1. 4 Tr ise=
Tnom=
Appr oxqb=yes RbM odel=MDS Lat er al=no Ff e=
Nk=
Ns=
I ss=
Rbnoi=
Fb=
Ab=
Kb=
Af = Kf = Tr =350 psec Pt f =40. 64 I t f =161. 4 mA Vt f =66 V Tf =2. 64 psec Xt f =228. 2
Fc=500E- 03 M js=0 Vjs=1 V Cjs=0 m F Xcjc=254. 7 mF M jc=214. 1E- 03 Vjc=718. 2 m V Cjc=18. 42 f F M je=112. 2E- 03 Vje=1. 36 V Cje=66. 22 f F I melt = I max=
Cco=
Cex=
Dope=
Rcm = Rcv=
Rc=9. 96 O hm Re=3. 312 O hm Rbm =46. 13 O hm I r b=15. 63 uA Rb=60 O hm Vbo=
G bo=
Cbo=
Nc=1. 95 C4=
I sc=14. 17 f A Kc=
Ke=
I kr =398. 4 uA Var =1 kV Nr =1. 054 Br =1. 027 Ne=1. 6 C2=
I se=1. 49E- 20 A I kf =208. 4 mA Vaf =1 kV Nf =1. 063 Bf =86. 21 I s=8. 26E- 25 A PNP=no NPN=yes
Fig. 3-12 Schematic of post simulation
The simulation parameter of bond-wire is reference A Variable Gain Low Noise Amplifier Design for IEEE 802.11 a 5 GHz U-NII Band by Bo-Cheng Chen of Chung-Hua University. The simulation parameter of bond-wire is Aluminum wire and the inductance is about 1.5nH. The transmission effect is reference CIC GaAs course text book.
Loss tan = conductivity/6.28*f*dielectric constant
ρ=108 ohm-cm
Substrate dielectric constant = 12.8
Thickness of Meatal:M1= 1um ；M2= 1.6 um
The post simulation results are as follow.
1. The input is AM signal as well and the modulation is 0.5. Amplitude is
5 mV.Fig. 3-13 Post transient simulation for input 0.7mV
Fig. 3-13 Post transient simulation for input 0.7mV (con)
2. The input is AM signal as well and the modulation is 0.5. Amplitude is
15 mV.Fig. 3-14 Post Transient simulation for 15mV input
Fig 3-14 Post Transient simulation for 15mV input (con)
The frequency of this design is 925 MHz. Depend on transmission line theory, λ/20 =16.216 mm. The chip size is 1mm X 1mm. It can satisfy the condition which have to under λ/20, and the result has been verifies by simulation. So this design has met the transmission line theory.
The process variation can surmount by control the bias.