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中 華 大 學 碩 士 論 文

題目:無線辨識系統之自動增益控制電路設計

Automatic Gain Control Circuit Design for Radio Frequency Identification System

系 所 別:電機工程學系碩士班 學號姓名:M09201003

范繼中 指導教授:田

誠 博士

中華民國 九十四年 七月

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中文摘要

現在RFID標籤、讀寫器所使用的頻率大概有5種,分別為135KHz以 下,13.56MHz,860M~932MHz(即UHF),2.45GHz以及5.8GHz,各有其 特色和缺陷。本篇是基於860~932 MHz 時因傳輸距離長,約Min 2~Max 10 公尺,所以有時標籤(tag)與讀卡器(Reader)感應時失敗。

其中一個原因是因為在標籤(tag)端的整體架構中通常都會有比較器存 在,而比較器要有好的雜訊免疫力時候就必須會降低靈敏度,而靈敏度

(sensitivity)好的時候,比較器的遲滯現象就會變的很差,整個標籤(tag)的 反應時間就會拉長,而造成 reader 端的誤判或者是反應速度變差。而解決 這種樣現象的方法有幾種解決方式,一是從軟體方面著手,改善其演算法 的方式,但是防碰撞的演算法不易實現,另外可以由硬體方面著手,在比 較器方塊之前加一級自動增益控制電路(Automatic Gain Control CKT,

AGC),以改善此現象,其中需要除了要注意電路的功能性完整以外,讓此 級自動增益空電路的固定輸出滿足後級比較器的輸入特性外,又可以使下 級的比較器具又好的雜訊免疫力為主的特性,以達到整體標籤(tag)具有好 的靈敏度(sensitivity),另外電路的複雜度不能太高,以兼顧成本上的考量。

本論文以 GCTC 2um 的製程來實現。

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Abstract

In the RFID system, the frequency of tag and reader to communicate has 135 KHz, 13.56 MHz, 860~932 MHz, 2.45 GHz and 5.8 GHz respectively. The application field and feature are different for each type. The frequency of this design is in the 860~932 MHz. This type of RFID is for long distance application. The distance of communicate is about 2~10 m. One of reason causes the communication fail between tag and reader is the comparator in tag.

The RFID tag usually has comparator; the noise rejection and the sensitivity are trade off condition. If the noise rejection is good than that means the sensitivity is worse and that will make the error happen. There are several solutions to solve this problem. The algorism is one of the solutions to solve this problem. But a suitable algorism is difficult to design.

The hard ware is another way to solve this problem. This thesis is design an AGC circuit add before the comparator to solve this problem. The AGC circuit can provide a stable input signal let comparator has good noise rejection and better sensitivity. The cost and complexity are the important factors to design this circuit. The AGC circuit of this thesis implement by GCTC 2um process.

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Acknowledgment

The author would like to thanks my teach Dr. Tien. This thesis won’t finish without him. My family, my friends, my classmate or who ever give hand to me.

Appreciate you all so much.

Lab S101 Chung Hua University, Hsinchu Chi-Chung Fan (Jeffrey Fan) 2005/7/18

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Contents

Abstract (Chinese) ... i

Abstract (English) ... ii

Acknowledgment ... iii

Contents ... iv

Figure Captions... vi

Table Captions ... vii

Chapter 1 Introduction ... 1

1-1 Background of Radio Frequency Identification System (RFID) ... 1

1-2 Review Radio Frequency Identification System... 2

1-3 Motivation ... 5

1-4 Thesis Organization... 6

Chapter 2 Automatic Gains Control Circuit ... 7

2-1 The AGC circuit applications in RFID tag ... 7

2-2 AGC Theory...11

2-3 The Generalized Block Diagram of AGC Loop ... 13

2-4 The Generalized Model of AGC Circuit ... 14

2-5 Typical AGC Circuit ... 26

Chapter 3 Circuit Design and Analysis... 30

3-1 Design Flow... 30

3-2 Circuits Specifications... 31

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3-3 Input Signal... 32

3-4 Model of Passive component... 34

3-5 Exponential characteristic ... 35

3-6 Circuit Analysis ... 37

3-7 Simulation Result ... 39

Chapter 4 Physically and Testing consideration ... 55

4-1 Layout consideration ... 55

4-2 Testing System setup ... 57

Chapter 5 Conclusions and Future Work ... 59

References... 60

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Figure Captions

Fig. 1-1 Basic structure of RFID system ... 3

Fig. 1-2 Classify of RFID system ... 3

Fig. 2-1 A basic structure of demodulator ... 7

Fig. 2-2 AGC’s transfer function curve ...11

Fig. 2-3 Common structure of an AGC Loop ... 13

Fig. 2-4 AGC loop after linearize ... 13

Fig. 2-5 Practical point of most general description of AGC system... 15

Fig. 2-6 Pseudo linear AGC system... 19

Fig. 2-7 AGC Model ... 21

Fig. 2-8 Dual Gate MOSFET for AGC... 26

Fig. 2-9 Dual Gate of MOSFET ... 28

Fig. 3-1 Design flow chart ... 31

Fig. 3-2 The structure of the AGC loop ... 33

Fig. 3-3 (a)ASK signal of EPC standard (b)Traditional AM signal ... 34

Fig. 3-4 (a) Amplitude Modulation (b) Amplitude Shift Keying ... 35

Fig. 3-5 AGC Circuit ... 37

Fig. 3-6 Load line of transistor Q1-Q4 ... 39

Fig. 3-6 Load line of transistor Q5-Q6 ... 40

Fig. 3-7 Transient Analysis with 0.7mV input... 41

Fig. 3-7 Transient Analysis with 0.7mV input (con) ... 42

Fig. 3-8 Fourier transform of every node with 0.7mV input... 43

Fig. 3-8 Fourier transform of every node with 0.7mV input (con) ... 44

Fig. 3-9 Transient Analysis with 1.5mV input... 44

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Fig. 3-9 Transient Analysis with 1.5mV input (con) ... 45

Fig. 3-10 Transient Analysis with 15mV input... 46

Fig. 3-10 Transient Analysis with 15mV input (con) ... 47

Fig. 3-11 Vin (dB) V.S. Vout (dB)... 48

Fig. 3-12 Schematic of post simulation ... 50

Fig. 3-13 Post transient simulation for input 0.7mV ... 51

Fig. 3-13 Post transient simulation for input 0.7mV (con)... 52

Fig. 3-14 Post Transient simulation for 15mV input ... 53

Fig. 3-14 Post Transient simulation for 15mV input (con)... 54

Fig. 4-1 Layout... 56

Fig. 4-2 Measurement setup ... 57

Fig. 4-3 PCB for testing... 58

Table Captions

Table 1 Parameter of simulation ... 32

Table 2 Summaries of the circuit specifications ... 33

Table 3 Vout and Vin... 48

Table 3 Vout and Vin (con) ... 49

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Chapter 1 Introduction

1-1 Background of RFID

In recent years automatic identification procedures (Auto-ID) have become very popular in many service industries, purchasing and distribution logistics, industry, manufacturing companies and material flow systems. Automatic identification procedures exist to provide information about people, animals, goods and products in transit.

The omnipresent barcode labels the triggered a revolution in identification systems some considerable time age, are being found to be inadequate in an increasing number of cases. Barcodes may be extremely cheap, but their stumbling block is their low storage capacity and the fact that they cannot be reprogrammed.

The technically optimal solution would be the storage of data in a

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everyday life is the smart card based upon a contact field; however, the mechanical contact used in the smart card is often impractical.

A contactless transfer of data between the data-carrying device and its reader is far more flexible. In the ideal case, the power required to operate the electronic data-carrying device would also be transferred from the reader using contactless technology. Because of the procedures used for the transfer of power and data, contactless ID systems are called RFID systems (Radio Frequency Identification).

Another factor contribution to its increasing popularity is the Wal-Mart and Tesco are mandating that all their suppliers adopt RFID.

1-2 Review Radio Frequency Identification System

RFID is hitting the mainstream now for a number of reasons. The recently developed electronic product code (EPC) and drive to lower tag costs, high performance are certainly the reasons. The specification of this thesis is following the EPC standard.

There are three main part of the RFID system. The tag (transponder) is affixed to the item being tracked. The reader (interrogator) is the device

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that reads the tag. Some readers can also write information to the tag. The third part of the system is the antenna.[1] Show as Fig. 1-1.

Fig. 1-1 Basic structure of RFID system

Another way to classify the RFID system or categorize RFID is by their function and memory size[2] as Fig. 1-2.

Fig. 1-2 Classify of RFID system

The Y-axis shows the different tag of function. EPC Global has

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defined five classes, which are outlined below.[3]

ƒ Class 0 are read only tags and pre-programmed by the manufacturer.

These are the simplest form of tags. The data is an alpha-numeric identification string. The factory determines the numbers and programs the tags; the factory then disables the memory from any further updates. Class 0 can also be used for EAS (electronic article surveillance) or anti-theft devices; they don’t have an ID number but announce their presence when passing through an antenna field.

ƒ Class 1 is a WORM tag (Write Once Read Many). They can be programmed by the manufacturer in the factory or by the user. The main idea is that data is written to the tag one time. These kinds of tags are usually used for simple product identification or for access cards or tokens

ƒ Class 2 is a read/write tag. Users have access to read and write into the tag’s memory. Class 2 tags typically have more memory and can be used as data loggers. For example, in a manufacturing line, the tag can be updated at every step of production

ƒ Class 3 tags are also read/write but can also contain onboard sensors, like temperature pressure, or motion. The sensor data is recorded into the tags memory. Since sensor readings must be taken in the absence of a reader, the tags as either semi-passive or active.

ƒ Class 4 are read/write but have integrated transmitters. These are the

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most sophisticated kind of tag. It can communicate with other tags and devices without the presence of a reader. To run independently it must contain it’s own power source or battery.

In this thesis, the specification of the design is following Class 1 of EPC Global standard RFID architecture.

1-3 Motivation

There are 5 classes in the RFID system of EPC standard specification.

In this thesis discuss the class 1 RFID tag. The frequency range is 860 MHz~930 MHz. As it is high frequency for long term transmits, so the distance is mainly reason to care about. In the EPC Global standard class 1regulation. The radio frequency (RF) communication interfaces specified for Class 1 tags operating in the frequency 860 MHz~930 MHz.

The intended free space communication range of the tags implemented to this specification is nominally greater than 3 meter with at least 2 meter at their worst orientation and no more than 10 at their best orientation.[4]

As the standard request, the circuit will become complicated and expansive. If a simple and cheap automatic gains control add into the tag will improve those problems to increase the competition of RFID costs.

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1-4 Thesis Organization

Thesis organization is divided into 5 chapters. Chapter 1 is the introduction. Chapter 2 is the AGC loop application, theory and the generally AGC circuits. Chapter 3 is the AGC circuit design flow, analysis and simulation result. Chapter 4 is physically consideration in chip layout and testing plan. Chapter 5 is the conclusion and the future work.

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Chapter 2

Automatic Gains Control Circuit

2-1 The AGC circuit applications in RFID tag

The demodulator is another key circuit block inside the analogue front end. Although the modulation schemes to use tin the reader might be different, some of them are amplitude modulation, and some of them are phase modulation. The analogue front end demodulator can demodulate is only in the form of amplitude change. So the demodulator is actually an edge detector.

Fig. 2-1 A basic structure of demodulator.

High Hystersis

Good Noise Rejection Worse sensitivity

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After the input carrier waveform is passed through a rectifier and envelop detector to extract envelop out. The low-pass filter after the envelope detector use to filter out the carrier ripple noise residue. Then the signal and its low pass filtered one is fed into a hysteresis comparator to generate the output.

The envelope detector is the simple and cheap form of AM demodulator. One problem comes along with the simple envelop detector is the no-linearity of the rectifier. And this will cause the output distortion.

However, the RFID system only transfers two logic value binary codes through the air. So the distortion of the envelope detector is not a critical problem. The other problem is the ripple and the negative peak clipping.[5]

The following analysis is based on single diode envelope detector. If we use full wave rectifier, the ripple would be decreased to half of the analysis.

Consider what happens when we have a carrier frequency,

f c

, and

use an envelope detector whose time constant, τ =R‚C. The time between successive peaks of the carrier will be T =

f c

1

. Between each carrier peak and the next the capacitor voltage will therefore be discharged to

V’ peak

= V

peak

EXP {-T/τ} (1)

Provided that T<<τ , the peak to peak size of the ripple will therefore be:

V   Vpeak /τ = Vpeak / ( f c τ)

(2)

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A sudden, large reduction in the amplitude of the input AM wave means that capacitor charge isn’t being fully charge by each carrier cycle peak.

The capacitor voltage therefore falls exponentially until it reaches the new, smaller peak value. To assess the effect, consider what happens when the AM wave’s amplitude suddenly reduces from V

peak

to a much smaller value. The capacitor voltage then declines according to

Vdrop = VpeakEXP {-t/τ} (3)

This produces the negative peak clipping effect where any swift reductions in the AM wave’s amplitude are finish and the output is distorted. Here chose the worst possible case of square wave modulation.

In practice the modulating signal is normally restricted to a specific frequency range. This limits the maximum rate of fall of the AM wave’s amplitude.

We can therefore hope to avoid negative peak clipping by arranging that the detector’s time constant τ <<

t m

where

t m

= 1/

f m

and

f m

is the highest modulation frequency used in a given situation.

1/

f c

<< τ <<1/

f m

(4)

That is clearly only possible if the modulation frequency

f m

<<

f c

.

Envelope detectors only work satisfactorily when we ensure this inequality is true.

Another key part of the circuit is the comparator. The comparator is a

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mature building circuit block and widely used in analogue and mixed signal ICs. The comparator to meet the specification of the RFID is not difficult to design. Let’s start from the dynamic range. As know, the input voltage level will be around several hundreds mill volts to several volts at different physical locations. The signal after the envelope detector and the low-pass filter should be in the same magnitude. The common mode input level to the comparator is from 100mV to 5V and the differential mode input level is about 80% of the common mode level.

Besides the dynamic rang, the hysteresis level is another important parameter of the comparator. When the analogue input signals are moving slowly or contain noise, the comparator outputs may oscillate at the input near the threshold point. Besides adding the power supply bypass circuits and better isolated the comparator from the other noisy circuits, hysteresis maybe added to further resist the oscillation during output transitions. As know, the high the hysteresis level, the better rejection of input noise and transition oscillations.

However, the high hysteresis level also means wore sensitivity and slow transition speed. Another words means, although the high hysteresis level will perform the better rejection of input noise and transition oscillation but the distance of RFID will reduce and slow transition speed.

The slow transition speed will cause the erroneous judgment in reader.

And the low hysteresis will cause the erroneous judgment as well by the noise injection. So it should better to set the hysteresis level “just” need level. It is harder to implement the “just” need level. If add an Automatic Gain control circuit block between the rectifier and comparator of the tag. Then the ripple and the negative peak clipping

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problems cause by rectifier and the hysteresis level problems cause by comparator will be solve easily.

In next few sections will going to design an Automatic Gain control circuit block.

2-2 AGC Theory

Many attempts have been made to fully describe an AGC system in terms of control system theory. So in this section will introduce the AGC theory including control theory involved behind the simple and primary idea of an AGC system. Before go into AGC theory. Fig. 2-2 shows the basically and ideal transfer function curve of AGC theory.

Fig. 2-2 AGC’s transfer function curve

Since an AGC is essentially a negative feed back system, the system can be described in terms of its transfer function. Those curves are the AGC’s transfer function curve. The ideal curve is illustrated in (1). The

(1)The ideal curve

(2)The Practical curve

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practical curve is illustrated in (2).

The ideal transfer function curve (1) has three statuses.

„ Status 1: Before the circuit reaches a threshold value V1 the AGC loop is disabled and the output is a linear function of the input.

„ Status 2: After the loop reaches the threshold value V1, the AGC loop becomes operative and maintains a constant output level until it reaches a second threshold value V2.

„ Status 3: After the AGC loop reaches the second threshold point V2. The AGC loop becomes inoperative again. This usually done in order to prevent stability problems at high levels of gain.

The practical curve should have the same situation in first and second part, but different situation in the third part. Because in fact the transistors will saturation and the magnitude of negative feedback increase continuous. So the output of AGC will decrease.

Many of the parameters of the AGC loop depend on the type of modulation used inside the system. If any kind of amplitude modulation is present, the AGC should not respond to any change in amplitude modulation or distortion will occur. Thus the bandwidth of the AGC must limited to a value lower than the lowest modulation frequency.

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2-3 The Generalized Block Diagram of AGC Loop

Fig 2-3. Common structure of an AGC Loop

Fig. 2-3 shows a common structure of an AGC loop. It is a negative feedback structure; the VGA output signal amplitude is extracted by a peak detector that will compare with the magnitude of reference voltage (V

ref

). The error signal or feedbacks gain control voltage (V

ctr

) control the gain of the VGA. From this Fig. it can be seen that the loop is not a linear loop because the performance of VGA is like a mixer. Thus, some extra blocks may need to be added to linearize the loop operation.

Vout

Vctr Vin

VGA Change the expression of VGA

log(Vout) = log (Vin) + log(V ctr ) The V ctr control the Gain of

VGA which performance

like a mixer in this loop.

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In Fig. 2-4, The VGA changes the expression to linearize the system.

Let the system can be analysis. The block which have been add is the logarithmic function, the VGA equation performs like an adder as follows log (V

out

) = log (V

in

x V

ctr

)

= log V

in

+ log V

ctr

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The HBT and the CMOS technology has different feature. In the HBT process, every transistor all has this character.

This character can reach this function easily. But in CMOS, it needs several block to approach, and more complicated. Because of the transconductance of HBT process is exponentially and the transconductance of CMOS process is square relation with current.

Because of that, by taking logarithmic function, the VGA equation performs linearly and analytic. So the HBT process had been chosen for this research.

2-4 The Generalized model of AGC Loop

As mention before, an AGC system is considered a nonlinear systems and it is very hard to find solutions for the nonlinear equation that arise during the analysis. Nevertheless, there are three models that describe the system’s behavior with a good degree of accuracy and are relatively easy to implement when the small signal transfer equations of the main blocks are know.

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Fig. 2-5 Practical point of most general description of AGC system

From a practical point of view, the most general description of an AGC system is presented in Fig. 2-5. The input signal is amplified by a variable gain amplifier (VGA), whose gain is controlled y an external signal Vc. The output from the VGA can be further amplified by a second stage to generate and adequate level of V

o

. Some the output signal’s parameters, such as amplitude, index of modulation or frequency, are sensed by the detector; any undesired component is filtered out and the remaining signal is compared with a reference signal. The result of the comparison is used to generate the control voltage (Vc) and adjust the gain of the VGA.

Fig. 2-5 could be described as the decibel-base linear model. In this model the variable gain amplifier (VGA) P has the following transfer function.

P = K

1

e

+aVc

(6)

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Where V

o

and V

i

are the output and input signal, K

1

is a constant and

a is a constant factor of the VGA. Following the signal path we find that

the logarithmic amplifier gain is:

V

2

= lnV

1

= lnk

2

V

o

(8)

Where K2 represents the gain of the envelope detector. Assuming that the output of the envelop detector is always positive (otherwise the logarithmic function becomes complex which translates in non working circuit), the output of the logarithmic amplifier is a real number and the control voltage becomes:

V

c

= F(s) (V

R

-V

2

) = F(s)(V

R

– lnk

2

V

o

) (9) F(s) represents the filter transfer function. Knowing that the VGA shows an exponential transfer function we can apply the logarithm function at both sides of the equation.

lnV

o

= aVc + ln V

i

K

1

(10)

Thus, the control voltage can be expressed as:

aV

c

= lnV

o

+ lnV

i

K

1

(11)

Using the expression for V

c

that we found before

lnV

o

[1+aF(s)] = lnV

i

+ aF(s)V

R

+lnK

1

-aF(s)lnK

2

(12) Since we are only interested in the output-input relationship, let K

1

and K

2

be equal to one. Thus, the above equation becomes:

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lnVo [1+aF(s)] = lnVi+ aF(s)VR (13) If V

o

and V

i

are expressed in decibels, we can use the following equivalence

ln Vo = 2.3log Vo (14)

Then,

ln Vo = (2.3/20) VodB =0.115VodB dB (15)

Finally, the equation that relates input and output (both in dB) can be rewritten as

) ( 1

V ) ( 7 . 8 aF(s) 1

V odB V idB R

s aF

s aF + +

= +

(16) This type of AGC system shows a linear relationship as long as input

and output quantities are expressed in decibels. From the last expression it is easy to see that the behavior of the system is determined by the a factor of the VGA and the filter F(s). F(s) is usually a low pass filter, since the bandwidth of the loop must be limited to avoid stability problems and to ensure that the AGC does not respond to any amplitude modulation that could be present in the input signal.

An important parameter in any control system is the steady-state error that is defined as

) (

ss lim e t

e = t → ∞

=

lim sE(s)

→ 0

l s

(17)

(29)

where E(s) is the error signal in the feedback path. Applying the definition given above th the AGC system we find that the position error constant is given by:

) 0 ( 1

1 e ss aF

= +

(18)

where F(0) is the DC gain of the F(s) block and a is the constant factor of the exponential law Variable Gain Amplifier (VGA). Thus, in order to maintain the steady state error as small as possible the DC gain of the F(s) block (usually a low pass filter ) must be as large as possible.

The simplest F(s) block that can be used in the system is a first order low pass filter whose transfer function is defined as follows:

B 1 s F(s) K

+

=

(19)

where K is the DC gain of the filter and B is the bandwidth. Using this expression in the equation of the steady state error we find that:

aK 1

1

= +

e ss

(20)

And the total DC output of the AGC system is given by:

V aK

+ +

= +

1

8.7aKV aK

1

V IDC R

ODC

(21)

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It can be seen that if the gain loop K is much greater than 1, the output is almost equal to 8.7V

R

and the steady state change in the input is greatly reduced. AGC systems that include a reference voltage inside the control loop are referred as delayed AGC.

The second model of an AGC system does not contain a logarithmic amplifier within the loop but still contains a exponential type VGA.

Despite the fact that the system’s complexity increases, it is still possible to find small signal models for small changes from a particular operation point.

Fig. 2-6 Pseudo linear AGC system

The block diagram shows in Fig. 2-6a can represent such system. It is important to notice that the VGA and the detector are the only nonlinear parts of the system. Assuming unity gain for the detector and the difference amplifier, the system can be reduced to the block diagram shown in Fig. 2-6b.

In the Fig. 2-6b, V

o

and V

i

are input and output signal respectively, F is the combined transfer function of the filter and difference amplifier.

The output voltage V

o

equal PV

i

, where P represents the gain of the VGA

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and it is a function of the control voltage V

c

. Following the signal path, we can see that the control voltage is given by:

V

c

= (V

r

-V

o

)F (22)

Since we are interested in the change in the output in the output voltage due to a change in the input voltage we can take the derivative of V

o

with respect to V

i

, therefore:

dVi Vi dP P dVi PVi

d dVi

dVo

= ( ) = +

(23)

The last derivative on the right side of the equation can be further developed applying the chain rule and using the equation for the control voltag3e, thus:

dVi F dVo dVc

dP dVi

dVo dVo dVc dVc

dP dVi

dVc dVc

dP dVi

dP = = = (− )

(24)

Therefore, the expression for

dVi

dVo

an be rewritten as:

dVc P FVi dP dVi

dVo

⎟=

⎜ ⎞

⎝⎛ +1 (25)

Alternatively

1

1

⎟ ⎠

⎜ ⎞

⎝ ⎛ +

= dVc

FVi dP Vi

dVi Vo

dVo

(26)

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It is clear that the loop gain is a function of the input signal, which translates into a relative degree of non-linearity and complicates the analysis of the transient response of the system, since the pole location is also dependant on the input signal, Nevertheless, it is possible to numerically evaluate the characteristic parameters of the loop if the P(Vc) function is know and a set of initial conditions is taken as an starting point.

All the AGC systems considered here provide a continuous sampling of the output signal and a continuous adjustment of the VGA. There are a few applications where the output signal is sampled at specific intervals of time and gain is adjusted only at those intervals. Those systems are known as pulse-type AGC systems and its analysis is usually performed using sampled data techniques.

The third model split every function of AGC into more block and describe the detail of AGC loop. Describe in Fig. 2-7.

Fig. 2-7 AGC Model

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By Fig. 2-7, the gain of the VGA, G (V

c

), is control with the voltage signal V

c

. The peak detector and loop filter form a feedback circuit that monitors the peak amplitude, A

out,

of the output signal V

out

and adjusts the VGA gain until the measured peak amplitude, V

p, is made

equal to the DC reference voltage, V

ref

.

The output of the AGC circuit is simply the gain times the input signal:

V

out

(t) = G(V

c

)V

in

(t) (27)

Since the feedback loop only responds to the peak amplitude, the amplitude of V

out

is

Aout =G(Vc)Ain (28)

where A

in

is the peak amplitude of V

in.

The equivalent representation model of an AGC circuit, as shown in Fig. 2-7, is derived follows. First, the feedback loop of an AGC circuit only operates on signal amplitudes, hence the AGC input and output signals are represented only in terms of their amplitudes A

in

(t) and A

out

(t), respectively. Second, since the VGA multiplies the input amplitude, A

in ,

by G(Vc) as shown in equation (28) an equivalent representation is

[ ( ) ]

⎭ ⎬

⎩ ⎨

⎧ ⎥⎦ ⎤

⎢⎣ ⎡ +

=

1

1 exp ln ln

v c in

v

out k

V A G k

A

(29)

The k

v1

is a constant with the same units as A

in

and A

out.

The AGC model in Fig. 2-7 uses equation (29), but duplicates the k

v1

exp() function inside and outside the outlined block so the x(t) and y(t) represent the

(34)

input and output amplitudes of the AGC, expressed in decibels within a constant of proportionality. Similarly, the z input shown is the value of V

REF

expressed in dB within a constant. The peak amplitude of V

out

(t) linearly and much faster the basic operation of the loop so that Vp = A

out

. Hence, the peak-detector is not explicitly shown in Fig. 2-7. Finally, the loop filter in Fig. 2-7 is shown as an integrator in Fig. 2-7, with

SC s G

H ( ) = M 2

(30)

The model in Fig. 2-7 helps to simplify the mathematical derivations and aids intuition. The output y(t) in Fig. 2-7 is given by

y(t) = x(t) +G(V

c

) (31)

The gain control voltage is derives as

[ ( ) ]

=

t

v y v z

M k e k e

C t G

Vc

0

) 2 (

1

2 ln

)

( τ

(32)

Taking the derivative of equation (31) and equation (32) we have

dt t dV dV dG Vc G dt dx dt

dy c

c

) ( )

( + 1

=

(33)

[ 1 2

ln

( ) ( ) ]

2 )

(

y t

z v

v e k e

C k GM dt

t

dVc

= − (34)

taking equation (34) substituting in equation (33), the following expression is obtained:

(35)

[ 1 2 ( ) ]

2 ln

) (

1 y t

z v M v

c

e k e C k

G dV dG Vc G dt dx dt

dy = + −

(35)

equation (35) describes a nonlinear system response of y(t) to an input x(t) unless constraints are place on the functions. The first step toward obtaining a linear relationship between x(t) and y(t) is to force the coefficient in the second term of equation (35) to equal a constant, kx,

C kx G dVc

dG Vc

G

M 2 = )

( 1

(36)

Equation (35) can be rewritten with equation (36) substituted in to yield

[ ]

REF x v

x

v z t x

v y x

e z v

v x

V dt k

t dx y k dt k

dy

e k dt k

e dx k

dt k dy

k e k dt k

dx dt

dy y t

+

= +

+

= +

− +

=

) (

ln ln

2

) 2 2 (

ln 2

1 ( )

(37)

By taking Laplace transform in equation (37)

)

( )

( )

( s kxk 2 Y s sX s

sY + v =

(38)

) 2

( ) ) (

(

v x k k s

s s

X s s Y

H = = +

(39) Equation (39) describes a first-order single time constant linear

system having a high pass response from the input x(t) to the output y(t).

The time constant,

τ

, of the system is given by

(36)

1 2 2

2

( )

1

1

⎥⎦

⎢ ⎤

= ⎡

=

M v

c c v

x

C k G dV

dG V G k

τ k

(40)

The classical criterion for constant settling time of the AGC loop assumes that GM2 and C are constant in equation (36) and equation (40), forcing the gain control function of the VGA to satisfy the following constraint:

) 1

( ) (

1 k G

dVc Vc dG Vc

G =

(41)

where k

G1

is a constant. Then

[ ]

Vc G kG

C Vc kG C

Vc kG

G G G

G

e k Vc G

e e

e Vc G

C Vc k Vc G

dVc Vc k

G Vc dG

dVc Vc k

G Vc dG

dVc k Vc dG Vc G

2 1

1 1

1 1 1

1

) (

) (

) ( ln

) (

) (

) (

) (

) ( ) (

1

=

=

=

+

=

=

=

=

+

∫ ∫

(42)

where

k G 2 = e c

is a constant of integration. One can easily determine that the gain in decibels (dB) should vary linearly with the control signal, Vc.

Using equation (42) for an exponential VGA gain characteristics and equation (40), the time constant of the AGC loop with a logarithmic amplifier included, is

(37)

2 1 2 log

exp

V G

M k k

G

= C τ −

(43)

With the constraints provided, the AGC loop will operate as a linear system in decibels for any change in input amplitude. By taking inverse of equation (43) and multiplying 2π , we can get the

C K K fT G M G v

π 2

2 1

= 2

(44) It is the locked bandwidth of AGC loop.

2-5 Typical AGC Circuit

For low frequency circuits the most common configuration consists of an operational amplifier and a voltage controlled attenuator. The basic voltage controlled attenuator consists of a fixed resistor connected in series with a field effect transistor working in the triode region. Such configuration is shown in Fig. 2-8.

Fig. 2-8 Dual Gate MOSFET for AGC

(38)

It can be shown that the output voltage is given by:

1 1

) 1

(

) 1

(

+ +

= +

L L

L L

in

out R R gdsR

gdsR V R

V

(45)

As Vgs approaches Vgs(off), gds approaches to zero an there is no attenuation of the input signal. If the value of R

L

is much higher that r

ds

(on) and R the above equation simplifies to :

Vin Rgds Vout = +

1 1

(46)

The output transconductance is given by:

) (

) (

OFF GS

GS OFF GS

V

V gdso V

gds

=

(47)

Where

) (

2

GS oFF DSS

V gds = I

(48)

Combining both equations:

] /

) [(

1 Rg dso V GS ( OFF ) V GS ( OFF ) Vout Vin

= +

(49)

The above circuit has two serious drawbacks, high harmonic distortion and limited signal handling capability. Both problems can be solved by feeding back on half of drain-source voltage to the gate, such modification simplifies the output transconductance equation to :

(39)

⎟ ⎟

⎜ ⎜

⎛ −

=

)

2 (

1

OFF

V GS

gdso Vc gds

(50)

Which is linear function of Vc.

Most of the above circuits can be used of to a few hundreds of megahertz, depending on the component selection, grounding, bypassing, impedance matching and physical layout of the circuit. Nowadays, with the high performance requirements of modern systems and devices it is advisable to study the most common techniques that are typically implemented in integrated circuit form.

The first device that can be found in integrated and discrete form is the Dual Gate MOSFET of DG-MOSFET. This device can be modeled as two MOSFET in cascode configuration with the input signal applied to the first gate (G1), and a second control signal applied to the second gate (G2). This second signal controls the gain of the overall stage and it is usually referred as the AGC signal.

Fig. 2-9 Dual Gate of MOSFET

The useful frequency range and electrical characteristics of the DGMOSFET is highly dependant on the technology used during the

(40)

fabricated of the device. Until now the best devices have been fabricated using HEMT (High Electron Mobility Transistor) technology for lower frequency applications.

Although DGMOSFET shows good high frequency performance, it is not widely used due to the lack of accurate models and a poor understanding of its characteristics.

(41)

Chapter 3

Circuit Design and Analysis

3-1 Introduction

In this chapter, the proposed AGC circuit for the application of ASK receiver has been presented, The components in the proposed AGC circuit are based on the fundamentals of the circuits, which have been presented in chapter 3, to improve the performance to meet the required specifications, In this chapter, we will compare the performance of the proposed circuit with the conventional circuits, as presented in chapter 2.

(42)

3-2 Design Flow

The design flow chart is depicted in Fig. 3-1. The design flow of used is the full custom design flow.

Specifications

Circuit Design

Simulations

Circuit Layout Satisfy Specifications?

DRC/LVS

Layout Verifications

GDSII

CIC Fabrication

Measurment/Verify

Satisfy Specifications?

Good Job !!

NO

Yes

Yes

Yes

NO

NO NO

Fig. 3-1 Design flow chart

(43)

The first step of flow is defined the specification of circuit which include frequency, output level, process technology… etc. The second step of flow is to select the circuit architecture. Simulation and verify the function of circuit by EDA tools is the third step of flow. In this design, ADS of Angilent is selected for simulator. After simulations finished, Cadence Corporation’s CAD tools to establish the circuit layout, design rule check (DRC). One thing need to mention is that the GCTC Corporation didn’t provide layout versus schematic (LVS) file. So LVS have to check by own self. Then Dracula and ADS are used for layout verification and post-layout simulation. The design technology is GCTC HBT process.

3-3 Circuit specifications

Process GCTC HBT 2um Amplitude Wave Carrier 925 MHz Signal 70KHz Ambient Temperature 25°C

Table 1 Parameter of simulation

The process is GCTC HBT 2um. The design is a block of RFID receiver chain. The ASK modulation is the receiving signal. The carrier of ASK modulation signal is 925 MHz for Electronic Product Code (EPC) standard. The signal is 70 kHz. The ambient temperature in simulation is 25°C in table 1. The electric parameter is list in table 2.

(44)

Symbols conditions Minimum Typical Maximum Unit

Supply Voltage Vcc 2.97 3.3 3.63 V

Supply Current Icc 16.2 18 19.2 mA

Maximum sensitivity SM VOD=3mV 700 uV

Detector output

Voltage VOD 3mV<Vin<88mV 8 9 10 mV

Range of AGC   A 20 dB

Output Voltage

Flatness   V 2 dB

Table 2 Summaries of the circuit specifications

The proposed AGC circuit system block diagram is depicted in Fig.

3-2. According to the specifications, the VGA provides the dynamic gain range. The capacitance achieves the loop filter and Peak detector.

Fig. 3-2 The structure of the AGC loop

The V ctr control the

Gain of VGA.

(45)

3-4 Input signal

Vin Vin

AM_ModTuned MOD2 Rout=50 Ohm Fnom=10 MHz ModIndex=0.3 AM_ModTuned

MOD1 Rout=50 Ohm Fnom=10 MHz ModIndex=0.3

VtSine SRC9

Phase=0 Damping=0 Delay =0 nsec Freq=70 GHz Amplitude=1 V Vdc=0 V V_1Tone

SRC8 Freq=925 MHz V=polar(100,0) mV V_1Tone

SRC4 Freq=925 MHz

V=polar(100,0) mV R

R19 R=50 Ohm

VtPulse SRC6

Period=14.84 usec Width=7.12 usec Fall=300 nsec Rise=300 nsec Edge=linear Delay=0 nsec Vhigh=1 V Vlow=-1 V

t

R R18 R=50 Ohm

Fig. 3-3 (a)ASK signal of EPC standard (b)Traditional AM signal

In the ADS, it provides the AM modulation tuned to generate ask modulation signal. The ask modulation signal may have problem in hspice. That is the reason why chose ADS to be the simulator for this design. In the Fig. 3-3(a), the output of ASK mod_tured is the ASK modulation signal. The carrier is a frequency domain source. The data signal is a sequence square wave. In the Fig. 3-3(b), it is the traditional Amplitude Modulation (AM) wave.

The carrier is the same as Fig. 3-3(a), but the data signal is a sine wave. The responds of circuit is the same of the EPC standard ASK signal and traditional AM signal. The process of simulation is faster if the ASK source is used liked Fig. 3-3(b). All the source in process of simulation is exactly the same as Fig. 3-3(b).

(46)

Fig 3-4 (a) Amplitude Modulation (b) Amplitude Shift Keying

Fig 3-4 (a) is amplitude modulation signal. Both carrier and signal is sinusoidal signal. Fig (b) is Amplitude shift keying signal. The standard of this signal has been notified in RFID regulation. Both Fig 3-4 (a) and Fig (b) are generated by ADS AM modulator and the modulation index is 0.5.

3-5 Exponential character

Before go to the circuit level. There is an important point had to notice and that would be exponential character. In an automatic gain control loop, to maintain its settling time independent of the input signal levels and a large dynamic control range, an exponential gain control characteristic is required.

However, in CMOS technology, it is difficult to realize the exponential or logarithmic function because of it inherent square or liner characteristics. Although the transistor operating in sub-threshold region has exponential characteristic, it is generally not preferred due to other unfavorable effects, such as noise and bandwidth. Thus, some of the

(47)

function.

The approximation errors of pseudo- exponential function to the ideal one is 5%. Alternatively, the Taylor’s series can be utilized to approximate the exponential function.

The approximation error of second-order approximation can be less than 5%. The each bipolar transistor in HBT process has own exponential function without any extra circuit to implement. From chapter 2, VGA is the kernel on determining the system performance in an AGC system.

According to equation (43), a VGA with exponential gain control characteristics is preferred for its large dynamic control range and constant loop settling time independent of the absolute gain.

It is easy to achieve exponential gain characteristics by using bipolar transistors. Because collector current characteristics of bipolar transistor is

V BE Vt

Ise Ic =

The voltage across base and emitter, V

BE

, can generate an exponential characteristic current in collector. Therefore, if exponential gain control is mandatory, parasitic bipolar device is the only solution due to the lack of intrinsic logarithmic characteristics of MOS device when it operates in strong inversion.

(48)

3-6 Circuit Analysis

‚ Pre-simulation

Fig. 3-5 AGC Circuit

In this design, the source signal is Amplitude Modulation (AM) signal which mentioned in previous section. The AM signal is a Double Side Band (DSB) signal. The DSB signal contains the carrier and sideband components which, when multiplied together, generate frequencies that include the original information signal. Capacitor C1 is a dc block capacitor and coupling capacitor. The AM modulation signal pass through C1. Transistor Q1 is common emitter amplifier. Q2 is a current source. There are few reasons for this combination. Here, the collector is connected to the positive supply and thus is at signal ground.

The input signal is applied to the base, and the output is taken from the

(49)

emitter.

The main purpose of the common collector circuit is to connect a source having a large input resistance to a load with a relatively low resistance. Since only a small fraction of the input signal appears between base and emitter, the emitter follower exhibits linear operation for a large range of input-signal amplitude. There is, however, an absolute upper limit imposed on the value of the output- signal amplitude by transistor cutoff. The output signal at the emitter is coupled via a large coupling capacitor C2 to next stage, C2 is dc block capacitor and a coupling capacitor as well.

The purpose of transistor Q3 and Q5 is to maintain the bias of transistor Q2, Q4 and Q6. The negative feedback magnitude will pull down or pull high the transistor bias. In this reason, fixed the bias point is necessary. So that transistor Q3 and Q5 is design for maintain the bias.

Basically transistor Q4, Q6 and Q7 are Variable Gain Amplifiers to amplify the modulation signal. Transistor Q4 and Q6 are common emitter connection to have a high output resistance and to provide substantial voltage and current gains and moderate value input resistance. The amplification is determinate by feedback magnitude.

Transistor Q7 is an amplifier between class AB and class B. The signals will recovery by transistor Q7 and a low pass filter. Resistor R

AGC

and capacitor C4 is a low pass filter to selects the information signal.

After the transistor Q7, the signal is then applied across capacitor C4.

Capacitor C4 have to large enough to ignore the rapid frequencies of the carrier but small enough to follow the voltage fluctuations of the waveform envelope.

(50)

3-7 Simulation Result

Fig. 3-6 Load line of transistor Q1

Fig. 3-6 Load line of transistor Q2 (con)

Fig. 3-6 Load line of transistor Q3 (con)

Fig. 3-6 Load line of transistor Q4 (con)

(51)

Fig. 3-6 Load line of transistor Q5 (con)

Fig. 3-6 Load line of transistor Q6 (con)

The load lines will adoptions with input signal. The input signal is Amplitude Modulation signal with 10 mV. The modulation index is 0.5.

There is an obvious feature in every load line curve and that is the load line cures will convergence into a fixed region because of negative feedback. The load line of transistor Q6 Fig. 3-6 shows this feature obviously.

The load line shows that transistor Q3 and Q5 are high impedance.

Transistor Q3 and Q5 maintains the load line stay in saturation region and won’t convergence to zero. The maximum sensitivity of this AGC circuit is 0.7 mV and list in specification.

The follow simulation result is every node of the circuit transient simulation

(52)

1. Minimum input signal 0.7mV Amplitude Modulation signal. The

modulation index is 0.5. The carrier frequency is 925 MHz, signal is 70K Hz.

Fig. 3-7 Transient Analysis with 0.7mV input

(53)

Fig. 3-7 Transient Analysis with 0.7mV input (con)

(54)

Fig. 3-8 Fourier transform of every node with 0.7mV input

(55)

Fig. 3-8 Fourier transform of every node with 0.7mV input (con)

2. Input signal 1.5 mV AM signal. The modulation index is 0.5.

Fig. 3-9 Transient Analysis with 1.5mV input

(56)

Fig. 3-9 Transient Analysis with 1.5mV input (con)

(57)

3. Input signal 15 mV AM signal. The modulation index is 0.5

Fig. 3-10 Transient Analysis with 15mV input

(58)

Fig 3-10 Transient Analysis with 15mV input (con)

(59)

4. Input signal (0.7 ~ 37 mV)

Auto Gain Control Performance

-60 -50 -40 -30 -20 -10 0

-70 -60 -50 -40 -30 -20

Vin (dBV)

Vout ( dBV)

Fig. 3-11 Vin (dB) V.S. Vout (dB)

Vout2 Vout1 Vout Vin Gain log Vin log Vout log Gain 2.9019 2.8981 0.0038 0.0007 5.428571 -63.098 -48.4043 14.69371 2.8966 2.8788 0.0178 0.0014 12.71429 -57.0774 -34.9916 22.08584 2.8881 2.8482 0.0399 0.002 19.95 -53.9794 -27.9805 25.99886 2.8863 2.8426 0.0437 0.0021 20.80952 -53.5556 -27.1904 26.36524 2.8844 2.8369 0.0475 0.0022 21.59091 -53.1515 -26.4661 26.68542 2.8824 2.8311 0.0513 0.0023 22.30435 -52.7654 -25.7977 26.96779 2.8803 2.8253 0.055 0.0024 22.91667 -52.3958 -25.1927 27.20303 2.878 2.8194 0.0586 0.0025 23.44 -52.0412 -24.642 27.39915 2.8757 2.8135 0.0622 0.0026 23.92308 -51.7005 -24.1242 27.57634 2.8732 2.8076 0.0656 0.0027 24.2963 -51.3727 -23.6619 27.7108 2.8707 2.8018 0.0689 0.0028 24.60714 -51.0568 -23.2356 27.82122 2.8681 2.7959 0.0722 0.0029 24.89655 -50.752 -22.8293 27.92278 2.8654 2.7856 0.0798 0.003 26.6 -50.4576 -21.9599 28.49763 2.8352 2.7365 0.0987 0.004 24.675 -47.9588 -20.1137 27.84514 2.8027 2.6914 0.1113 0.005 22.26 -46.0206 -19.0701 26.9505 2.7712 2.6548 0.1164 0.006 19.4 -44.437 -18.6809 25.75603 2.742 2.6249 0.1171 0.007 16.72857 -43.098 -18.6289 24.46918 2.7156 2.6 0.1156 0.008 14.45 -41.9382 -18.7408 23.19736 2.6918 2.5805 0.1113 0.009 12.36667 -40.9151 -19.0701 21.84505 2.6706 2.5644 0.1062 0.01 10.62 -40 -19.4775 20.52249 2.6517 2.5516 0.1001 0.011 9.1 -39.1721 -19.9913 19.18083

Table 3 Vout and Vin

(60)

2.6348 2.5408 0.094 0.012 7.833333 -38.4164 -20.5374 17.87893 2.6198 2.5313 0.0885 0.013 6.807692 -37.7211 -21.0611 16.66 2.6058 2.523 0.0828 0.014 5.914286 -37.0774 -21.6394 15.43805 2.5939 2.5136 0.0803 0.015 5.353333 -36.4782 -21.9057 14.57249 2.5831 2.5026 0.0805 0.016 5.03125 -35.9176 -21.8841 14.03352 2.5739 2.4905 0.0834 0.017 4.905882 -35.391 -21.5767 13.81434 2.5652 2.4789 0.0863 0.018 4.794444 -34.8945 -21.2798 13.61477 2.5575 2.4684 0.0891 0.019 4.689474 -34.4249 -21.0024 13.42248 2.5508 2.4588 0.092 0.02 4.6 -33.9794 -20.7242 13.25516 2.5448 2.4503 0.0945 0.021 4.5 -33.5556 -20.4914 13.06425 2.515 2.417 0.098 0.022 4.454545 -33.1515 -20.1755 12.97607 2.5338 2.4368 0.097 0.023 4.217391 -32.7654 -20.2646 12.50088 2.529 2.4311 0.0979 0.024 4.079167 -32.3958 -20.1843 12.21143 2.5245 2.4263 0.0982 0.025 3.928 -32.0412 -20.1578 11.88343 2.52 2.4211 0.0989 0.026 3.803846 -31.7005 -20.0961 11.60446 2.5148 2.4173 0.0975 0.027 3.611111 -31.3727 -20.2199 11.15282 2.509 2.414 0.095 0.028 3.392857 -31.0568 -20.4455 10.61131 2.5031 2.4109 0.0922 0.029 3.17931 -30.752 -20.7054 10.04666 2.497 2.409 0.088 0.03 2.933333 -30.4576 -21.1103 9.347228 2.4657 2.4 0.0657 0.035 1.877143 -29.1186 -23.6487 5.469947 2.4607 2.3984 0.0623 0.036 1.730556 -28.8739 -24.1102 4.763711 2.456 2.397 0.059 0.037 1.594595 -28.636 -24.583 4.053006

Table 3 Vout and Vin (con)

Fig 3-10 is the cure of different output due to different input and table 3 record the parameter. The dynamic turning range is about 20 dB. The maximum sensitivity is about 0.7 mV when output is 3 mV. The output voltage flatness is about 2 dB.

(61)

‚ Post-simulation

(Including Bonding wire and Transmission line effect)

VB2 VC3 VC2

Vin

Vout VC1

VE1 VB1

VB4

VC6 VC5

VC4

VB7 VB5 VB6

V_1Tone SRC4 Fr eq=925 M Hz V=polar ( 1. 5, 0) m V

R R1 R=250 O hm MSABND_MDS

Bend11

M=0. 5 Angle=45 W=25 um Subst =" M Sub1"

M LI N TL13 L=115. 5 um W=25. 0 um Subst =" M Sub1"

MSABND_M DS Bend10

M=0. 5 Angle=45 W=25 um Subst =" M Sub1"

M LI N TL12 L=43. 5 um W=25. 0 um Subst =" MSub1"

Q 8_model Q 2 Q 8_model Q 1

MLI N TL14 L=75 um W=25. 0 um Subst =" M Sub1" M TEE

Tee1

W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"

MTEE Tee2

W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"

M LI N TL15 L=31. 0 um W=25. 0 um Subst =" M Sub1"

R R4 R=500 O hm M SABND_M DS Bend14

M =0. 5 Angle=45 W=25 um Subst =" MSub1"

MLI N TL16 L=172 um W=25. 0 um Subst =" M Sub1"

M SABND_M DS Bend12

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

M LI N TL17 L=134. 5 um W=25. 0 um Subst =" M Sub1"

M LI N TL11 L=70. 72 um W=25. 0 um Subst =" MSub1"

M SABND_M DS Bend9

M =0. 5 Angle=45 W=25 um Subst =" MSub1"

MLI N TL10 L=166. 1 um W=25. 0 um Subst =" M Sub1"

MSABND_M DS Bend8

M=0. 5 Angle=45 W=25 um Subst =" M Sub1"

MLI N TL9 L=120. 82 um W=25. 0 um Subst =" M Sub1"

M SUB M Sub1

Rough=0 um TanD=1. 24 m T=1 um Hu=1. 0e+036 um Cond=1. 0E+50 M ur =1 Er =12. 8 H=100 um MSub

M easEqn M eas3 VBE1=VB1- VE1 VCE1=VC1- VE1 E q n Me a s

M LI N TL22 L=76 um W=25. 0 um Subst =" MSub1"

M LI N TL47 L=262. 3 um W=25. 0 um Subst =" M Sub1"

M TEE Tee9

W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"

M LI N TL20 L=141 um W=25. 0 um Subst =" M Sub1"

Cap_150x150 Cap19

21

R R38 R=50 O hm

AM_M odTuned M O D1 Rout =50 O hm Fnom =10 MHz M odI ndex=0. 3

Vt Sine SRC1

Phase=0 Dam ping=0 Delay=0 nsec Fr eq=70 kHz Amplit ude=1 V Vdc=0 V

R R17 R=18 kO hm

M TEE Tee8

W3=25. 0 um W2=25. 0 um W1=25. 0 um

Subst =" M Sub1" M LI N

TL46 L=94. 3 um W=25. 0 um Subst =" MSub1" M TEE

Tee7

W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"

MLI N TL45 L=56 um W=25. 0 um

Subst =" M Sub1" M TEE

Tee6

W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" MSub1"

M LI N TL44 L=38. 2 um W=25. 0 um Subst =" M Sub1"

M LI N TL29 L=15. 3 um W=25. 0 um Subst =" MSub1"

MSABND_MDS Bend23

M=0. 5 Angle=45 W=25 um Subst =" M Sub1"

MLI N TL43 L=664. 9 um W=15. 0 um Subst =" M Sub1"

M SABND_M DS Bend22

M =0. 5 Angle=45 W=25 um Subst =" MSub1"

M LI N TL42 L=84. 1 um W=25. 0 um Subst =" M Sub1"

Q 10_model Q 9 M LI N TL41 L=47. 51 um W=25. 0 um Subst =" M Sub1"

M TEE Tee5

W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"

R R15 R=295 O hm

M LI N TL40 L=315. 6 um W=15. 0 um Subst =" MSub1"

Q 9_m odel Q 8 M LI N

TL39 L=74 um W=15. 0 um Subst =" M Sub1"

R R14 R=160 O hm M LI N TL37 L=10 um W=25. 0 um Subst =" M Sub1"

MSABND_MDS Bend21

M=0. 5 Angle=45 W=25 um Subst =" M Sub1"

M TEE Tee4

W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" M Sub1"

M LI N TL38 L=106. 5 um W=15. 0 um Subst =" M Sub1"

MLI N TL36 L=22. 5 um W=25. 0 um Subst =" M Sub1"

M CRO SO Cr os1

W4=25. 0 um W3=25. 0 um W2=25. 0 um W1=25. 0 um Subst =" MSub1"

R R12 R=500 O hm M LI N TL35 L=135. 4 um W=25. 0 um Subst =" M Sub1"

M SABND_M DS Bend20

M =0. 5 Angle=45 W=25 um Subst =" MSub1"MLI N TL34 L=151 um W=15. 0 um Subst =" M Sub1"

M SABND_M DS Bend19

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

M LI N TL33 L=60 um W=25. 0 um Subst =" M Sub1"

Q 8_m odel Q 7

M LI N TL32 L=212. 92 um W=25. 0 um Subst =" M Sub1"

M SABND_M DS Bend18

M =0. 5 Angle=45 W=25 um Subst =" MSub1"

M LI N TL31 L=319. 5 um W=15. 0 um Subst =" M Sub1"

M SABND_M DS Bend17

M =0. 5 Angle=45 W=25 um Subst =" MSub1"

M LI N TL30 L=75. 5 um W=25. 0 um Subst =" M Sub1"

M SABND_M DS Bend16

M =0. 5 Angle=45 W=25 um Subst =" MSub1"

M LI N TL28 L=34. 5 um W=25. 0 um Subst =" M Sub1"

R R13 R=500 O hm M LI N TL27 L=15. 3 um W=25. 0 um Subst =" M Sub1"

Cap_150x150 Cap18

21

M LI N TL26 L=55 um W=25. 0 um Subst =" MSub1"

M LI N TL25 L=15. 3 um W=25. 0 um Subst =" M Sub1"

M LI N TL24 L=168 um W=25. 0 um Subst =" M Sub1"

R R5 R=500 O hm

M SABND_MDS Bend15

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

M LI N TL23 L=70 um W=25. 0 um Subst =" MSub1"

Q 8_m odel Q 3 MLI N

TL21 L=105. 4 um W=25. 0 um Subst =" M Sub1"

M LI N TL19 L=145 um W=25. 0 um Subst =" MSub1"

M LI N TL18 L=105 um W=25. 0 um Subst =" M Sub1"

R R3 R=500 O hm

M SABND_M DS Bend13

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

M SABND_M DS Bend7

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

MLI N TL8 L=201. 1 um W=25. 0 um Subst =" M Sub1"

M SABND_M DS Bend6

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

M LI N TL7 L=52. 4 um W=25. 0 um Subst =" MSub1"

M SABND_M DS Bend5

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

BJT4_NPN BJT1

M ode=nonlinear Tr ise=

Temp=

Region=

Ar ea=

M odel=Q 2P0X9 BJT4_NPN BJT12

M ode=nonlinear Tr ise=

Temp=

Region=

Ar ea=

M odel=Q 2P0X9 MLI N

TL6 L=102. 4 um W=25. 0 um Subst =" M Sub1"

M LI N TL4 L=78. 9 um W=25. 0 um Subst =" M Sub1"

M SABND_M DS Bend3

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

M LI N TL5 L=32. 3 um W=25. 0 um Subst =" MSub1"

MSABND_MDS Bend4

M=0. 5 Angle=45 W=25 um Subst =" M Sub1"

M LI N TL3 L=48. 8 um W=25. 0 um Subst =" MSub1"

M LI N TL2 L=50. 5 um W=25. 0 um Subst =" M Sub1"

Cap_200x200 Cap10

21

M SABND_M DS Bend2

M =0. 5 Angle=45 W=25 um Subst =" MSub1"

MLI N TL1 L=119. 4 um W=25. 0 um Subst =" M Sub1"

M SABND_M DS Bend1

M =0. 5 Angle=45 W=25 um Subst =" M Sub1"

V_DC SRC5

Vdc=3. 3 V C

C6 C=39 nF R

RAG C R=22 O hm

Tran Tran1 MaxTimeStep=1.5 usec StopTime=30 usec StartTime=0.0 nsec

TRANSI ENT

BJT_Model Q 2P0X9

AllPar am s=

Xt i=4 Xt b=- 1 Eg=1. 4 Tr ise=

Tnom=

Appr oxqb=yes RbM odel=MDS Lat er al=no Ff e=

Nk=

Ns=

I ss=

Rbnoi=

Fb=

Ab=

Kb=

Af = Kf = Tr =350 psec Pt f =40. 64 I t f =161. 4 mA Vt f =66 V Tf =2. 64 psec Xt f =228. 2

Fc=500E- 03 M js=0 Vjs=1 V Cjs=0 m F Xcjc=254. 7 mF M jc=214. 1E- 03 Vjc=718. 2 m V Cjc=18. 42 f F M je=112. 2E- 03 Vje=1. 36 V Cje=66. 22 f F I melt = I max=

Cco=

Cex=

Dope=

Rcm = Rcv=

Rc=9. 96 O hm Re=3. 312 O hm Rbm =46. 13 O hm I r b=15. 63 uA Rb=60 O hm Vbo=

G bo=

Cbo=

Nc=1. 95 C4=

I sc=14. 17 f A Kc=

Ke=

I kr =398. 4 uA Var =1 kV Nr =1. 054 Br =1. 027 Ne=1. 6 C2=

I se=1. 49E- 20 A I kf =208. 4 mA Vaf =1 kV Nf =1. 063 Bf =86. 21 I s=8. 26E- 25 A PNP=no NPN=yes

Fig. 3-12 Schematic of post simulation

The simulation parameter of bond-wire is reference A Variable Gain Low Noise Amplifier Design for IEEE 802.11 a 5 GHz U-NII Band by Bo-Cheng Chen of Chung-Hua University. The simulation parameter of bond-wire is Aluminum wire and the inductance is about 1.5nH. The transmission effect is reference CIC GaAs course text book.

Loss tan = conductivity/6.28*f*dielectric constant

ρ=10

8 ohm-cm

Substrate dielectric constant = 12.8

Thickness of Meatal:M1= 1um ;M2= 1.6 um

(62)

The post simulation results are as follow.

1. The input is AM signal as well and the modulation is 0.5. Amplitude is

5 mV.

Fig. 3-13 Post transient simulation for input 0.7mV

(63)

Fig. 3-13 Post transient simulation for input 0.7mV (con)

(64)

2. The input is AM signal as well and the modulation is 0.5. Amplitude is

15 mV.

Fig. 3-14 Post Transient simulation for 15mV input

(65)

Fig 3-14 Post Transient simulation for 15mV input (con)

The frequency of this design is 925 MHz. Depend on transmission line theory, λ/20 =16.216 mm. The chip size is 1mm X 1mm. It can satisfy the condition which have to under λ/20, and the result has been verifies by simulation. So this design has met the transmission line theory.

The process variation can surmount by control the bias.

參考文獻

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