Placing power clamps can increase CDM level of a device. The challenge is to place mini-mal number of power clamps with most gain in CDM level. There are several power clamp placement methodologies adopted in industry. One approach is to place power clamp uni-formly across the device. Such approach provides a low resistance path for the surge current uniformly across the device, however, it requires large number of power clamps which is very inefficient. Another intuitive approach is to place one power clamp next to each internal I/O pins. However, such approach still neglects internal I/O pin density of the device. In this chapter, we first analyze the effect of power clamp placement to CDM level. Based on the analysis, a clamp placement algorithm is proposed to efficiently increase device’s CDM level using minimal number of power clamps.
4.1 Peripheral Power Clamp Placement
During a CDM event, the current discharge path begins from VDD(VSS) power domain through the power clamp to the VSS(VDD) power domain and discharge through the stress pin. Long discharge path creates larger voltage drop across the device due to longer resistive path. Larger voltage drop across the device implies that two power domains have higher probability to suffer larger voltage drop.
Chapter 4. Clamp Placement 16
Charge stored on e
Vdd stripe
Charge stored on Vdd stripe and Gnd Stripe
Charge stored on e
Vdd stripe
Charge stored on Vdd stripe and Gnd Stripe
Charge stored on Vdd stripe and Gnd Stripe
Charge stored on Vdd stripe and Gnd Stripe
(a) Vdd Stripe voltage distribution Module 1
Module 2
Domain B
Charge stored on Vdd stripe
Charge stored on e
Vdd stripe
Charge stored on Vdd stripe and Gnd Stripe
Charge stored on e
Vdd stripe
Charge stored on Vdd stripe and Gnd Stripe
Charge stored on Vdd stripe and Gnd Stripe
Charge stored on Vdd stripe and Gnd Stripe
(b) Gnd Stripe voltage distribution
Figure 4.1: Voltage distribution of VDD and VSS power domain at the instant when stress pin is grounded. Power clamp is positioned right next to the stress pin. The two white rectangles represent two individual power domains. (a) Voltage distribution of
VDD power domain. (b) Voltage distribution of VSS power domain.
Thus, a general solution to reduce the current discharge path is to identify the location of the stress pin and place a power clamp right next to the stress pin. Placing power clamp next to the stress pin instantly discharge the current from VDD and VSS power domain which simultaneously reduces the discharge path. In addition, this placement method has a side benefit which is having similar voltage distribution for VDD and VSS power domain. Similar voltage distribution between VDD and VSS power domain implies that distance between two power domains linearly correlates to the voltage drop between two power domains. This is a desirable factor to the designers because reduction of cross voltage between two power domains can be simply achieved by moving two power domains closer. Fig. 4.1 illustrates the voltage distribution of VDD and VSS power domain when a power clamp is placed right next to the stress pin. However, since there is no known method to predict which of the external I/O pins will be grounded, a safe approach is to place a power clamp around the peripheral boundary of the device with uniform spacing.
Placing power clamps around the peripheral boundary is a general approach to improve CDM level of the device regardless of the module’s location.
Conventional clamp placement methodology places a power clamp next to each internal I/O pins. The concept behind methodology is to minimize the current discharge path between transceiver and receiver. However, since each power clamp reduces voltage drop of
Chapter 4. Clamp Placement 17 neighboring range within a certain radius, placing a power clamp next to each internal I/O pin is redundant for regions with high pin density. By adopting k-means clustering [15], we propose a clamp placement algorithm that minimizes the distance from internal I/O pin to its nearest power clamp. The problem is constrained such that power clamp can only be placed at the location of internal I/O pin. We define the constrained power clamp placement problem as follows.
The constrained power clamp placement problem. Given the location of internal I/O pins P = {p1, p2, ..., pk}, place minimal number of power clamps such the distance from each internal I/O pin to its nearest power clamp is minimized. Power clamp can only be placed at the location of internal I/O pins.
Regarding to Fig.4.1, a sharp voltage drop at VSS domain can be observed at peripheral boundary. The reason behind the sharp voltage drop is because stored current converge at the stress pin which is located at the peripheral boundary and thus creating large cross voltage between VDD and VSS domain. Thus, during a CDM event, modules that are placed near the peripheral boundary are prone to suffer larger voltage drop compared to modules located in center of device. To motivate more power clamps placed at peripheral boundary, a set of pseudo I/O pins are added around the peripheral boundary.
4.2 Power Clamp Placement Based on Pin Location
Algorithm2 describes the procedure to place power clamps by adopting clustering tech-nique. The algorithm begins by selecting pin closest to the bottom left corner as the initial location to place the first power clamp. In Line 10-23, after a new power clamp is placed, each pin updates the distance to its nearest power clamp. In line 24, pin with the maximum distance to its nearest power clamp is selected as the next location to place power clamp. The iterative process terminates until the maximum distance from each internal I/O pin to the nearest power clamp is less than a pre-define range. In this work, α is set to 80.
Chapter 4. Clamp Placement 18
Algorithm 2 Power Clamp Placement Based on Pin Location Input: Location of internal I/O pins P = {p1, p2, ..., pk} Output: Location of power clamps C = {c1, c2, ..., cm}
1: MINDIST(pi) = ∞ ∀ i = 1 → k
2: j = 1
3: C ← ∅
4: pbl ← pin closest to the bottom left corner
5: Add new power clamp cj at location of pbl
18: if MINDIST(pi) ≥ MAXDIST then
19: pmaxdist = pi
20: end if
21: end if
22: end for
23: end for
24: Add new power clamp cj at location of pmaxdist
25: j = j + 1
26: Add location of cj to C
27: while MAXDIST > α
28: do
29: Assign pin pi to nearest power clamp cj
30: Place cj at location of pin pi closest to the mean location of cluster
31: while Position of all power clamps cj ∈ C is stable
Chapter 5
Experimental Results
Table 5.1: Power Network Synthesis setting
Parameter Settings
Sheet Res. 0.17 Ohm/µm2
CPERSQDIST 3.10E-04 pF/µm2
ME1 Wire Width 0.3 µm
ME2 Wire Width 10 µm
ME1 Wire Spacing 12 µm
ME2 Wire Spacing 12 µm
Via Res. 0.01
Diode Res. 1 Ohm/µm
Cross Vol. Clamp 1.5 V
Clamp Res. 1E-05 Ohm
In this chapter, experimental result of the proposed framework is presented. The entire framework is implemented with standard C++ language and compiled using g++ 4.1.2.
Experiments are performed on an Intel XEON E5620 machine running at 2.4Ghz. GSRC benchmark [16] is used as input benchmarks. The number of power domains and driving voltage for each module are initially determined. Table 5.2 shows the detail of the input benchmarks. In Table 5.2, P. D. 2-Pin Net stands for number of 2-Pin nets between two power domains. I. Module stands for number of module within the voltage island and E.
Module stands for number of external module voltage island connects to.
We reference UMC65 technology file and lists the value of parameters in Table 5.1. The discussion on experimental result discusses the effect of the power clamp placement to CDM level.
Chapter 6. Experimental Results 20
5.1 Analysis on Power Clamp Placement
To evaluate effectiveness of different power clamp placement methods, five floorplans are generated for each testcase. The floorplans are generated using default configuration which only considers area and HPWL of the netlist. Four power clamp placement methods are applied. The first method, uniform, adopts conventional approach which places power clamp with uniform spacing. The second method, periphery, places power clamp with uniform spacing only at the peripheral boundary of the device. The third approach, pin+periphery, places one power clamp next to each internal I/O pin and around the peripheral boundary. The fourth method, cluster+periphery, places power clamps based on clustering analysis and around the peripheral boundary.
Table 5.3 shows the performance of different power clamp placement methods. The uni-form method serves as the baseline approach to evaluate the other three methods. The purpose of periphery method is to achieve similar voltage distribution between VDD and VSS power domain when an external I/O pin is grounded. Table5.3shows that periphery method can achieve 95% to 103% of CDM level while using only 32% to 44% number of power clamps compared to the baseline approach. The pin+periphery method can ef-fectively improve CDM level of the design on all six designs by 1% to 14% compared to the baseline approach. However, redundant power clamps is placed for design with high density of internal I/O pins such as n200 and n300, the pin+periphery method requires an additional 44% and 19% number of power clamps.
To address the issue of redundant power clamp insertion, the cluster+periphery method aims to minimize the maximum distance from each internal I/O pin to its nearest power clamp. From Table 5.3, the cluster+periphery method achieves equivalent amount of improvement on CDM level while inserting average of 31% less power clamps compared to the pin+periphery method.
Chapter 6. Experimental Results 21
Table5.2:Detailoftheinputbenchmarks.(P.D.standsfornumberofpowerdomainsexcludingchippowerdomain.Netstands fornumberofnetlist.P.D.2-Pinnetstandsfornumberofcrosspowerdomain2-pinnets.InternalI/OPinstandsfornumberof internalI/Opins.I.Modulestandsfornumberofinternalmoduleswithinthevoltageisland.E.Modulestandsfornumberofexternal modulesconnectedtothevoltageisland.) P.D.NetP.D.InternalP.D.1P.D.1P.D.1 2-pinNetI/OPinI.ModuleE.ModuleI.ModuleE.ModuleI.ModuleE.Module n101021182591916NULLNULL n303033495526213212115 n5050348512343228218225 n1001003885413521621518 n2002003158510384336229223 n3003003189314699444330229
Chapter 6. Experimental Results 22
Table5.3:ComparisononCDMlevelandnumberofpowerclampsusingUniform,Pin+PeripheralandCluster+Peripheral.(CDM standsforCDMlevel.C.#standsfornumberofpowerclamps.) PinClusterPinCluster UniformPeripheral++UniformPeripheral++ PeripheralPeripheralPeripheralPeripheral CDMC.#CDMC.#CDMC.#CDMC.#CDMC.#CDMC.#CDMC.#CDMC.# n10 1154788139630161239161239 n100
1106876104229107763106148 21598901537321590411590412142881153033188166187954 3604925752962538625383483573443032477665481446 41861941847281800371800374179777176629197163196948 51770991664311750401750405184783184235190469193254 Max.186194184728180037180037Max.483573443032477665481446 Min.60492575296253862538Min.106876104229107763106148 G.M.1.001.000.950.321.010.421.010.42G.M.1.001.000.990.401.080.841.080.64 n30
175591686358096181055 n200
11423781407351501116145360 27729569537755637555722144811899352059116196859 311899510763911946411976031830751889292221108203656 43948754339583655826041387821335391623119161665 59149183236937629375651289801341361585113146058 Max.118995107639119464119760Max.2144811899352221108203656 Min.39487543395836558260Min.1289801335391501116145360 G.M.1.001.000.990.411.100.691.100.63G.M.1.001.000.980.441.121.441.070.75 n50
151188508355377854057 n300
18221138204387014185177 231894309363247831057210611201013431291140130776 3143594137341152184152168312191131156391305136129174 46868863037691806736149801191008441060139105181 594688126235160378162255511041231093451191142115579 Max.143594137341160378162255Max.12191131156391305136130776 Min.31894309363247831057Min.8221138204387014185177 G.M.1.001.001.030.411.140.881.130.66G.M.1.001.000.980.361.101.191.090.66
Chapter 6
Conclusion
In this work, we propose a CDM optimization framework that can be employed at design stage. During a CDM event, the instant that peak current occurs is when transistors are most vulnerable to a CDM event. To defend against a CDM event, we first propose a CDM simulation model that can be solved efficiently using static power analysis. While conventional methods on clamp placement generally insert redundant power clamps, we propose a clamp placement algorithm based on clustering analysis which can effectively minimize number of power clamps while achieving better CDM level.
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