The accurate and integrated clock generator is needed to the switching regulator.
Although the structure can be designed easily such as ring oscillator, but the huge frequency variance while supply voltage changes may affect system stability. The clock generator for the high switching DC-DC buck converter in current domain control is shown in Fig. 45 [22].
Fig. 45. Schematic of the clock generator circuit.
The operational steps of clock generator are described as follows. At first, assumed that the prior state of the node CLK1=0 and CLK2=1, the transistors MP1, MN2 turn on and the transistors MP2, MN1 turn off. Then the constant current ICLKcharges to the capacitor C1 and the capacitor C2 discharges to ground by flow into the MN2 path. Before the comparator CMP1 changes the state, both of the comparators output is zero. And it doesn’t affect the output of S-R latch because both of input voltage is zero meaning the output of S-R latch keeps the prior state. Once the voltage V1 is bigger than reference voltage VREF, the comparator CMP1 changes state, and the input set S of S-R latch is logic high. Finally, the node CLK1 changes to logic high and the node CLK2 changes to logic low. Secondly, as the node CLK1=1, CLK2=0, contrary the capacitor C1 is discharged by MN1 and charges the capacitor C2, and finally the result backs to the first step that the node CLK1 changes to logic low and the node CLK2 changes to logic high. The actions between the first and the second step will operate repeatedly. Consequently, the clock generator with fixed frequency is provided and can be designed by the following formula.
1 2 out of phase clock signals to the one shot circuit which is sown in Fig. 46 respectively. The main function of one shot circuit is generating a pulse signal when the clock signal is changing from low to high. And the pulse signal determines the minimum duty ratio of system, generally speaking, the delay time of pulse signal is ten percent of system switching period.
Finally, using the logic OR gate to combine the output of one shot circuits. The doubled switching clock can be obtained. For 20MHz switching frequency design, just generating 10MHz 50% duty out of phase clock signals can provides a 20MHz clock signal. Eventually, the one shot signal with fixed and doubled clock is provided and the one shot signal can set the converter to turn on the power PMOSFET in the beginning of every switching cycle.
Fig. 46. Schematic of the one shot circuit.
When designing the clock generator, it must be take care of two things. At first, the
current. Then the output of comparator is both logic high and affects the normal operation if only use the S-R latch. The additional logic added on the S-R latch is shown in Fig. 47. The purpose of additional logic is preventing the non-defined case caused by S-R latch and making the clock generator in the incorrect function. Therefore, the non-defined function is defined as “SET” state, that is the CLK1=1, CLK2=0, after adding the additional logic of S-R latch. And the clock generator gets in normal operation. By the way, the pulse generator circuit of current domain buck converter is also using this kind of structure [6]. The truth table of S-R latch with additional logic is also listed in TABLE VII.
Fig. 47. The additional logic with S-R latch.
Another important component of clock generator is voltage comparator. Because operating at 20MHz switching frequency. The comparison speed of voltage comparator must be as fast as possible. For high switching frequency design, the voltage comparator is shown in Fig. 48 [23] and the structure is described as follows.
TABLE VII. THE TRUTH TABLE OF THE S-RLATCH WITH ADDITIONAL LOGIC
State S R Q(n+1) QB(n+1)
Set 1 0 1 0
Hold 0 0 Q(n) QB(n)
Reset 0 1 0 1
Priority set 1 1 1 0
Fig. 48. Schematic of the voltage comparator.
Because of Current-mode comparators have higher speed, larger bandwidth, and lower supply voltage requirements compared to their conventional voltage-mode counterparts [25].
The Fig. 48 shows the circuit schematic of the designed current comparator block. The circuit consists of a V-to-I converter, a current subtractor and a current comparator at the last stage [24]. The difference between VPOS and VNEG inputs of the comparator is converted into error current Ierr at the output of the subtractor stage. The error current Ierr is then applied to the first current source inverting amplifier, which uses a resistive feedback to reduce its input and output resistance [25]. These small resistances reduce the voltage swing at nodes V1 and V2, which causes faster transient response time in the following inverting amplifiers. The simulation result of voltage comparator is shown in Fig. 49. Operating at switching frequency 20MHz, the rise time and fall time delay is lower than 4n second when there is a 0.1V voltage difference between the positive and negative input stage.
The simulation result of clock generator shows in Fig. 50, where the frequency of 50%
duty out of phase cycle signals are about 10MHz, and the one shot time of set signal is about 5n second. Therefore the combinational clock signal is doubled to 20MHz and the one shot is
about 10% of the clock cycle. Finally, the detail clock information between different kinds of process corner and supply voltage is listed at TABLE VIII.
Fig. 49. The simulation results of voltage comparator.
Fig. 50. The simulation results of clock generator.