Complexity Analysis

Here, this thesis analyzes the complexity of the number of variables and constrains in our ILP formulation. Firstly, the number of variables is proportional to the number of patterns (i.e., |UPPS K( ) |); the number of columns in every dot plane; the upper bound of the minimum depth UB. This thesis denotes the number of patterns as |P|. Besides, the minimum depth upper bound UB is proportional to

log( (h d0) ) . Therefore, the complexity of the number of variables is

0 0

(log( ( )) ( ) | |)

O h d w d  P . Secondary, this thesis makes the analysis of the number

of the constraints in the following. Similar to the complexity of the number of variables, the number of the constraints is proportional to the number of columns in every dot plane and the minimum depth upper bound UB. Therefore, the complexity of the number of the constraints is O(log( (h d₀))w d( ₀)).

3.7 Post-processing for Area Minimization

This thesis describes a post-processing procedure to reduce the area overhead without losing delay optimality. This post-processing procedure is described as two phases. Before detailing this two phases, we would define redundant matches firstly.

A match m on the dot plane d_s is redundant iff h d( _s1) does not increase while all dots matched by m can be matched by p instead. In Phase I, we would delete all ₁ redundant matches under the dot plane d_z1 on the penultimate stratum when the minimum depth of the delay optimal compress tree is z. Figure 3.3(a) shows that a redundant match match p( ₂,1) exists on the dot plane d₁1,3, 2,1, based on the specific cover cover({(p₁, 0), (p₂,1), (p₃, 2), (p₁,3)}). Figure 3.3(b) shows that the depth of the compressor tree does not increase after deleting the redundant match

( 2,1)

match p on d1. According to this phenomenon, this thesis presents Phase I of the post-processing procedure for area minimization. Firstly, we check the existence of redundant matches under the dot plane d_z1. If there is a redundant match m, it will be deleted from the compressor tree, e.g., the two dots of the match match p( ₂,1) on the dot plane d1 can be matched by p1 instead such that they can be passed through from the dot plane d to the dot plane ₁ d , as shown in Figure 3.3(b). Otherwise, Phase I ₂

is finished. As shown in Figure 3.4, the process stated above is one of the iterations in Phase I; therefore, this post-processing procedure will repeat the process until there is no redundant match on the penultimate stratum.

Practically, basic logic cells on modern FPGAs are flexible. In other words, modern FPGAs employ two single-output LUTs with shared inputs as shown in Figure 3.5. In general, this kind of circuits is called two-output LUTs. We observe that two-output LUTs can map two single-output Boolean functions simultaneously if the two functions satisfy two conditions: (i) the summation of the two function’s distinct variables should be fewer than or equal to the physical-input constraint denoted as PIC (PIC8 on Altera Stratix IV, and PIC5 in Xilinx Vertex V, e.g., PIC is equal to 6 in the example as shown in Figure 3.5), and (ii) the summation of the LUT size of the two functions should be fewer than or equal to the

Figure 3.4 Phase I of the post-processing procedure.

physical-capacity constraint denoted as PCC (PCC64 on Altera Stratix IV, and 64

PCC in Xilinx Vertex V [1, 2]) . Actually, PCC is equal to 2^K, where K is the input constraint of a LUT. Besides, a two-output LUT can map a single output function if the number of variables of the function is K (K = 6) as shown in Figure 3.5.

Moreover, we can merge the two distinct LUTs among all strata if the two functions mapped by these two distinct cells satisfy PIC and PCC. Suppose we want to map the two prime patterns p₄ 1, 2_p as shown in Figure 3.6(a) (i.e., PIC6 ,

64

PCC ), and then we can map the two patterns onto four two-output LUTs as shown in Figure 3.6(a). Obviously, the summation of the number of inputs of LUT 2 and 4 is equal to 6 which is fewer than PIC, and the summation of the LUT size is equal to 2³2³ which is fewer than PCC. Hence, we can merge LUT 2 and LUT 4 into a single LUT as shown in Figure 3.6(b). In Phase II, we merge the distinct LUTs to map different patterns if these two functions mapped by them satisfy PIC and PCC.

5-inpt LUT

5-inpt LUT

6-inpt LUT

Figure 3.5 A two-output LUT with shared inputs.

LUT1

LUT 3 LUT 2

LUT 4

p

p

p

p

LUT 2 LUT 1

LUT 3

(a) (b)

Figure 3.6 (a) The mapping before Phase II. (b) The mapping after Phase II.

Chapter 4

Experimental Results

4.1 Experimental Information

We implement DOCT and the GPC heuristic [14] in C/C++ language on a workstation with an Intel Xeon 2-GHz processor and 16 GB main memory under the Centos 5.2 operating system. Besides, an open source package, lp_solve 5.5.13, is used to solve the linear formulations. A set of benchmark circuits is evaluated including three Radix-4 unsigned Booth-encoded multipliers (8 by 8 and 16 by16), multiplier accumulators (MAC), discrete cosine transformation (DCT) [20], finite impulse response filters (FIR), and motion estimations (ME). The input of each compressor trees is extracted from the simulation result produced by MATLAB Simulink toolbox. All compressor trees in our experiments are directly synthesized without pipelined.

Table I illustrates the detail information of the benchmark circuits. In Table I, Column 1 shows the variety of our benchmark circuits. Column 2 and Column 3 show the width and the height of the input dot plane, respectively. Column 4 shows the number of dots in the input dot plane.

4.2 Parameters Setup

We implement two compressor tree synthesis algorithms DOCT and the GPC heuristic. The following is the setting of parameters in our experiment.

DOCT: Compressor tree synthesis using DOCT described in preceding sections under K6 and H3. This thesis supposes that DOCT is evaluated on Altera Stratix IV. Thus, the physical input constraint (PIC) is set to 8 and the physical capacity constraint (PCC) is set to 64. The compressor tree produces three outputs summed by ternary adder.

GPC: Compressor tree synthesis using the generalized parallel counter (GPC) heuristic. In the GPC heuristic, there are three parameters: (i) M is the input

constraint of GPC patterns (the input constraint of LUTs in the targeted FPGA, e.g., 6 for Altera Stratix IV, and Xilinx Vertex V), (ii) N is the output constraint of GPC patterns, and (iii) k is the number of inputs of the final CPA (i.e., k is equal to H). In our experiments, M is set as 6; N is set as 4; k is set as 3. The setting is the same as [14].

4.3 Experimental Results

In our experiment, we compare both the depth and area produced by DOCT to that by the GPC heuristic. Table II, III, and IV show the experimental results under

TABLE II

different input constraints of LUTs: K 5, K6, and K7, respectively. In Table II, III, and IV, Column 2 illustrates upper bounds of all benchmark circuits.

Column 3 and Column 4 illustrate the depth of compressor trees produced by DOCT and the GPC heuristic. Meanwhile, Column 5 and Column 6 illustrate the area in terms of LUTs on Altera Vertex Stratix IV produced by DOCT and the GPC heuristic. Compared to the GPC heuristic, DOCT has 27% less depth with 17%

fewer LUTs under K5; 32% less depth with 21% fewer LUTs under K6; and 20% less depth with 2% fewer LUTs under K7. For all benchmark circuits, the GPC heuristic was finished in few seconds; meanwhile, DOCT was finished in 500 seconds.

It is evident that DOCT always have better or the same result in depth compared to the GPC heuristic. The reason is that DOCT consider all combinations of all prime patterns for constructing a compressor tree. Although DOCT does not outperform the GPC heuristic in area for every case, it provides smaller area on

Chapter 5

Conclusions and Future Work

A delay optimal compressor tree synthesis algorithm, DOCT, has been presented in this thesis. Since the infinite set of patterns can be superseded by the finite set of prime patterns without loss of delay optimality, DOCT adopts an ILP-based methodology to map prime patterns onto the compress tree with the minimum depth and utilizes a post-processing procedure to minimize area overhead.

Therefore, DOCT can authentically archive compressor trees with minimum depths by all prime patterns under the input constraint of a LUT. On average, compressor trees produced by DOCT have 32% less depth and 21% fewer LUTs than those produced by the GPC heuristic on modern technologies.

Although DOCT has made a progress in reducing area overhead compared to the GPC heuristic, we believe that there is still room for improvement. In the beginning, we have put the area cost in the cost function of ILP formulation.

Unfortunately, the run time of DOCT is too long and unacceptable. But according to the result of some smaller case, DOCT considering area cost in the cost function could archive around 50% fewer LUTs than that does not consider. Yet, we believe that the research of reducing area optimally is worth being performed in the future.

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