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Chapter 2. FFT algorithm

2.2. Complexity comparison

From table 2.1 [3] and table 2.2 [4], the multiplication and addition of radix-8 have the lowest complexity compared with radix-2 and radix-4. In table 2.1 radix-8 consist of constant multiplications and real multiplications. The constant multiplication can be implemented by shifters and adders whose hardware is simpler than a real multiplication. Table 2.3 [5] is the complexity equation of multiplications and additions.

The radix-8 type1 algorithm is the original radix-8 FFT algorithm. In radix-8 type2

algorithm, we replaced multiplication of

1

W

8

into p additions. According to our discussion in the next section, we set the parameter p to be 3 here. But according to the large silicon area and power hungry features of complex number multiplier , we only focus on the number of real number multiplications. In figure 2.1, radix-8 type2 has the lowest computational complexity, so we choose radix-8 type2 as the building block to implement 128-points fft.

Table 2.1 Multiplicative comparison [3]

Table 2.2 Multiplications and additions comparison [4]

Real Multiplications Real Additions

N Radix-2 Radix-4 Radix-8 Radix-2 Radix-4 Radix-8

Table 2.3 Equation of multiplications and additions comparison [5]

algorithm Real Multiplication Real Addition

Radix-2 8

Figure 2.1 Complexity comparison of real number multiplication of table 2.3

Figure 2.2 Complexity comparison of real number addition of table 2.3 In figure 2.4, it illustrate the inter connection in radix-2 FFT. We make 8 radix-2 butterfly to be an unit, then 16-point FFT needs 4 times recursive operation which needs 3 times decimation. The number of switch shows in equation (02), where N is number of points, r is radix-r, and stage is total stage. The parameter p is the number of switch in different radix. In table 2.4, we show radix-r from radix-2 to radix-16 when N is equal to 128. In figure 2.4, we show that radix-8 can provide the less number of switches. Because the number of switches is related to the complexity of the design, we chose radix-8 architecture to implement this design.

( )

1 1 1

Number of switch N stage p

r

  

= × − × − +  (02)

Figure 2.3 Illustration of inter connection in FFT.

Table 2.4 The number of switch.

Figure 2.4 Number of switch versus radix-r.

2.3. 128-point FFT algorithm

To develop FFT algorithms, set N in eq. (1) to be power of 2 and consider

computing separately the even-numbered frequency samples and the odd-numbered

frequency samples. The even-numbered frequency samples are

1 This can be expressed as

( / 2 1) 1 With a substitution of variables in the second summation in (4), than

( / 2 1) ( / 2) 1 Finally, because of the periodicity of

2rn From (6) is the (N/2)-point DFT of the (N/2)-point sequence obtained by adding the first half and the last half of the input sequence. Adding the two halves of the input sequence represents time aliasing, consistent with the fact that in computing only the even-numbered frequency samples, that are under sampling the Fourier transform of

x(n). In the same way, we can get the odd-numbered frequency points, given by

( / 2 1)

From (6) and (7) let N=128, than the even-numbered frequency samples and the odd-numbered frequency samples can be divided as eq. (8).

63

Equation (7) is the 64-point DFT of the sequence obtained by subtracting the second half of the input sequence from the first half and multiplying the resulting

Figure 2.6 Signal flow graph of 128-point FFT algorithm.

In figure 2.5, a radix-2 butterfly operation is illustrated. In figure 2.6,the signal flow graph of DIF 128-point FFT algorithm is listed. The first stage is radix-2 butterfly with a twiddle factor multiplication, then the 64-point FFT is the second stage of 128-point FFT. The signal flow graph of DIF 64-point FFT algorithm is listed in figure 2.7, we can observe that the 64-point FFT consists of two stages radix-8

butterfly and twiddle factor multiplication. Then we will introduce the 64-point FFT algorithm at the next section.

Figure 2.7 Signal flow graph of 64-point FFT algorithm.

2.4. 64-point FFT algorithm

We use radix-8 FFT algorithm to conduct 64-point FFT algorithm. The N point DFT is rewrite at eq. (10), where N is the power of 8.

1

0

( ) ( ) , 0,1 1,

N

nk N n

X k x n W k N

=

′ =

′=

N

=8 , a

a

N

(10) Using the value transform, let

k

′ =8

k

+

l

and

n

= +

n

1

n

2.

0, , 1

Equation (13) can be considered as two-dimensional DFT. One is 8-point DFT and the other is N/8-point DFT as shown in figure 2.8. Then, by decomposing the N/8-point DFT into the 8-point DFT recursively through a-1 times, where a is equal to log8N, we can complete the N-point radix-8 DIF FFT algorithm. In (13), the 8-point DFT which is the basic operation unit, is shown in figure 2.9. A butterfly is also an essential arithmetic component in an FFT processor. In figure 2.9, it is clearly seen that seven complex multipliers are need in a butterfly unit by direct mapping approach to implement 8-point DFT. Radix-8 FFT algorithm is seldom used in single-memory FFT architecture, because the hardware cost of its butterfly unit is too high to implement. In order to implement radix-8 FFT algorithm more efficiently, we follow the radix-23 DIF FFT algorithm.[4]

Figure 2.8 signal flow graph of N-point radix-8 FFT

Figure 2.9 Radix-8 DIF butterfly.

To decompose butterfly of radix-8 DIF FFT algorithm into three steps and apply the radix-2 index map to the radix-8 butterfly.

From equation (13)

Figure 2.10 Three step radix-8 DIF butterfly.

In (14), we use the radix-2 index map to divide the 8-point DFT into three steps.

Figure 2.10 shows the butterfly of the three-step DIF radix-8 FFT. The twiddle factors,

W and

81

W at the first step are trivial complex multiplication, because they

83 can be written as 22

(

1

j )

and 22

(

− −1

j )

. Thus, a complex multiplication with one of the two coefficients can be computed using additions and a real multiplication, whose hardware can be realized by four shifters and three adders. We will introduce the hardware architecture in further chapters.

In eq. (14), let N=82=64 and

{ }

3 2 1

0,1, , 7, , , 0,1

k

= 

l l l

( ) ( )

In eq. (15), the 64-point FFT is based on two stage radix-8 butterfly and it needs 49 times complex multiplications exclude from

W ,

81

W and

83

W . The signal flow is

80 shown in figure 2.7.

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