5.1 Conclusion
Viterbi decoders are widely used in communication systems as decoding convolutional codes which provide a superior error correction capacity while maintaining a reasonable coding complexity and computing resource. However, power dissipation in modern VLSI designs has become a more critical issue in communication systems and System-on-Chip (SoC) era which have emphasized low power features due to the limited battery life. For this reason, the goal of this work is to implement a low power survivor memory unit (SMU) hard macro for Viterbi decoders.
In this thesis, a fully custom SMU hard macro, which is composed of a lot of registers, with low power feature for Viterbi decoders is presented. We choose the register-exchange based SMU as our topology. After introducing relative low power registers, we proposed our low power low swing static edge-triggered latch (ETL) which is very suitable for the register-exchange SMU design due to its less clock loading and fewer transistors number at power and area domain. We not only simulate proposed low swing static ETL in 0.13 um CMOS process, but also in 90 nm CMOS process especially interesting in leakage power dissipation. The detailed simulation results and discussions are addressed in Chapter 3.
Then we based on our proposed low swing static ETL to construct the low power SMU hard macro by means of the fully custom design flow, and the
5.2 Future Works
Although we have completed a low power SMU hard macro design for Viterbi decoders, to integrate this work with other synthesized blocks of Viterbi decoders by means of EDA tools is another challenge. Besides, the data-gating and clock-gating techniques which are very powerful in low power applications could be utilized in implementation of SMU for saving input and clock buffers’ power dissipation.
In modern VLSI designs the demand of design for testability (DFT) is more and more important to the past because the larger chip size and complexity are disadvantageous to the yield of manufacture. Adding scan chain is an effective and widely used way in cell-based design flow for DFT. However, in our fully custom SMU hard macro we can not add scan mechanism easily. The DFT issue in this work needs to be solved in the future.
Besides, the complex interconnect routing between each stages in proposed SMU design occupied more area than stages itself. Besides, the fully custom routing takes a lot of time and is not an efficient solution while the system specifications of Viterbi decoders change. If we build the proposed low power low swing static ETL into the standard cell library, not only the complex interconnect routing could be done efficiently but also the DFT problem could be solved easily by means of convenient EDA tools in the cell-based design flow.
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