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A memory collision free algorithm to achieve high parallel SISO decoders for turbo-decoding has been presented. The high parallel collision free Turbo decoder has been implementation for VLSI architecture using the UMC-90nm standard CMOS cell library. As a result, the throughput of 32-memory-collision free turbo-decoding could achieve up to 169.25Mbps with clock frequency 200MHz, which is faster than that of serial SISO decoder 12Mbps

This paper introduces a memory collision free algorithm using simulated annealing heuristic method for parallel Turbo decoder, in which a highly parallel structure is available. By applying memory collision free algorithm, we proposed two area-efficient extrinsic memory schemes achieving lower hardware cost for high parallel Turbo decoder structure. The experimental results in UMC 0.13-μm CMOS process show that the organization of our proposed extrinsic memory without extrinsic non-linear quantization can achieve around 40% memory area reduction for the 32-SISO parallel Turbo decoder relative to conventional extrinsic storage using dual port RAM for the Turbo code of CCSDS standard. On the other hand, the organization of our proposed extrinsic memory with extrinsic non-linear quantization can further achieve around 46%

memory area reduction for the 16-SISO parallel Turbo decoder.

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