Conclusion …

I. Introduction

As down-scaling the VLSI technology in to deep sub-100nm regime, the degradation of circuit performance and power consumption (both DC and AC) and fast increasing manufacturing cost are the main challenges for continuous technology evolution. The down-scaling MOSFET into sub-100nm usually gives significant lower drive current per unit gate width at lower bias voltage and the high density interconnect may dominate the total circuit delay of circuit speed. The manufacture cost also increases rapidly with scaling down. To overcome the performance degradation in MOSFETs, strain silicon channel with high mobility is needed (shown in Figure 1.1). It has also been used by AMD (Advanced Micro Devices) and Intel in their new microprocessors performance [1].

There are many ways to introduce the strain to silicon. The stress is typically introduced by lattice mismatching of hetero-epitaxial layers (shown in Figure 1.2), or by polysilicon or nitride deposition, or upon completion of the device process, by bending [2]-[4]. We thin down Si substrate thickness (tsub) to 30µm and mount on plastic. Due to high flexibility of thinner t_sub on plastic, larger tensile strain (proportional to1t_sub² ) can be applied for further improvement. In this thesis, we have used the process and device simulation (TCAD) to analyze the measured device characteristics of 0.18µm MOSFETs before and after bending. The measurement data

of 16-fingers 0.18µm MOSFET is taken as reference data to calibrate the simulation

program. The result from TCAD will be modeled towards the measurement data.

Moreover, we use TCAD to conjecture several probably stress field and find it which agree with actual stress distribution. By using the well calibrated TCAD for 0.18µm MOSFET and strain field, we predict the RF performance of 0.18µm MOSFET under

tensile strain. The simulation procedure which contains process and calibration are described in Chapter III to VI. The effects of tensile strain is simulated and the

phenomenon of higher drive current, RF current gain and lower NF_min are shown in Chapter VI as mechanical strain 0.18µm MOSFET increases. Such RF improvement

is due to the increased g_m, RF gain and cut-off frequency (f_t) by applied mechanical

tensile strain. Finally, we compare simulation data with measurement data for strain 0.18µm MOSFET in the last part of Chapter VI. The trend from TCAD is fit in with

measurement data. Conclusion of the thesis is presented in Chapter VIII.

Figure 1.1 Mobility versus technology scaling trend for Intel process technologies

(Ref. IEEE Trans Electron Device, vol 51, No 11, Nov 2004)

Figure 1.2 The traditional approach where strain is applied into the channel from the bottom using strain-silicon on relaxed SiGe.

(Ref.http://www6.tomshardware.com/business/20050419/amd_chip_

production-06.html)

II. Literature Review

2.1 MOSFETs Electron Inversion Layer Mobilities

The electron mobilities of the MOSFET inversion layers based on a reciprocal sum of three-scattering mechanisms, phonon, Coulomb, and surface roughness scattering, and it is explicitly dependent on temperature and transverse electric field.

To clarify the discussion, a schematic is given in Figure 2.1.

The channel mobility at 300 K is smaller than that at low temperatures and less dependent on the roughness of surface or oxide charge density. At these temperatures, phonon scattering dominates at low and intermediate fields. The channel mobility is much more dependent on oxide charge and inversion layer carrier concentration at it and peaks at intermediate transverse fields. At low field, the mobility increases as oxide charge scattering decreases because of carrier screening. At carrier concentrations above the peak, the mobility decreases as surface-roughness scattering predominates. The mobility is very temperature dependent at low inversion layer carrier concentrations and temperature independent at high surface inversion carrier concentrations.

The physical modeling of channel mobility is complicated further by the formation of energy sub-bands in the dimension perpendicular to the channel [6]. The constant energy surface of electrons in silicon is shown schematically in Figure 2.2.

A detail explanation of the carrier distribution in these sub-bands and sub-band energies and cross sections as a function of temperature and transverse electric field has been given recently by Lin [6]. He shows by calculations that atT ≤77K ^the majority of carriers in the channel are in the lowest sub-band. This sub-band has the smallest cross section perpendicular to the channel and, thus, the carriers are more tightly confined at the silicon-silicon dioxide interface. Their tight confinement results in mobility degradation caused by oxide-charge scattering at low transverse fields and surface roughness scattering at high fields. At around room temperature and low fields, the carrier mobility is less affected by surface-roughness scattering as more carriers are in the higher, wider sub-bands and phonon scattering dominates. However, at high fields E_eff ≥8×10⁵V/cm , the sub-bands are separated further in energy and there are more carriers in the lowest, shallower sub-band, so surface roughness scattering becomes important.

Fig. 2.1 The channel mobility dependence on inversion layer carrier density Ns as a function of temperature

(Ref. IEEE Trans Electron Device, vol 36, No 8, Aug 1989)

Fig. 2.2 Silicon showing six conduction band valleys in the (100) direction of momentum space

(Ref. IEEE Trans Electron Device, vol 38, No 8, Aug 1991)

2.2 MOSFETs Electron Inversion Layer Mobility Enhancement under Tensile Strain

It is known that the sub-band structure of 2-dimensional (2D) carriers in the inversion layer substantially affects the electrical characteristics of Si MOSFETs through inversion layer mobility, µ^, and inversion-layer capacitance, Cinv. Thus, the optimum design of the sub-band structure in the inversion layer can allow to

significantly improve the MOSFET performance. This paper [7] presents the concept of a sub-band structure engineering to enhance the current drive.

Principle of Sub-band Engineering

G

m, in the triode region, which is still a good indicator of the current drive in short-channel MOSFETs in terms of velocity overshoot, is described by

gc

Thus, higher

µ

and larger Cinv, which increases the gate-channel capacitance, Cgc, are required for higher current drive of MOSFETs. From this viewpoint, the 2-fold valleys in the sub-band structure of 2D electrons on a (100) surface are the optimum e1ectronic system, as schematically shown in Figure 2.3. This is because the 2-fold

valleys have the lower effective mass parallel to the Si/SiO₂ interface, which increases

µ

^, and the higher effective mass perpendicular to the interface, which increases Cinv.

The occupancy of the 2-fold valleys is determined by the sub-band energy difference between the 4-fold and the 2-fold valleys,

∆ E

₀

( = E

₀^'

− E

₀

)

. As a result, the

occupancy of the 2-fold valleys is not sufficiently large for bulk MOSFETs at room temperature because of the smaller

∆ E

₀. This fact means that, if

∆ E

₀can be increased, the occupancy of the 2-fold valleys and the resulting Gm, can also been enhanced.

Fig. 2.3 Sub-band structure of 2D electrons on (100) and the

characteristics of two kinds of the sub-bands

(Ref. IEEE Electron Devices Meeting, Dec. 1997, Page(s):219 - 222)

2.3 Thermal Noise in MOSFETs

Noise sources --- Drain Current Noise

The dominate noise source of RF MOSFETs is the drain current noise which is expressed as:

f g KT

i_nd² =4

γ

_d0∆ Equation 2-3 where gd0 is the drain-source conductance at zero VDS. The parameter γ has a vale of unity at zero V_DS and, in long channel devices, decrease toward a value of 2/3 in saturation [8]. Some measurements show that short-channel devices exhibit noise considerably in excess of values predicted by long-channel theory, sometimes by an order of magnitude in extreme cases. Some of the literature attributes this excess noise to carrier heating by the large electric fields commonly encountered in such devices.

In this view, the high fields produce carriers with abnormally high energies. No longer in quasi-thermal equilibrium with the lattice, these hot carriers produce abnormal amount of noise. But in contrast to other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs by our good measurements. The details will be illustrated in the section three.

Substrate Thermal Noise

Figure 2.4 shows a simplified picture of how the thermal noise associated with

the substrate resistance can produce measurable effect at the main terminals of the devices. At frequencies low enough that we may ignore C_cb (open), the thermal noise of R_sub modulates the potential of the back gate, contributing some noisy drain current:

f g KTR

i

_nd² _,sub

= 4

_{sub mb}²

∆

Equation 2-4 Depending on bias conditions – and also on the magnitude of the effective substrate resistance and size of the back-gate transconductance – the noise generated by this mechanism may actually exceed the thermal noise contribution of the ordinary channel charge. In this regime, layout strategies that reduce the substrate resistance have a noticeable and beneficial effect on noise.

At frequencies well above the pole formed by C_cb and R_sub, however, the substrate thermal noise becomes unimportant, as is readily apparent from inspection of the physical structure and the corresponding frequency-dependent expression for the substrate noise contribution [8]:

C f

The characteristics of many IC processes are such that this pole is often around 1 GHz. Excess noise produced by this mechanism consequently will be most noticeable below about 1 GHz.

substrate C

cb

R

sub

drain source

gate

Fig. 2.4 Substrate thermal noise

Figure 2.5 shows a simplified picture of how the thermal noise associated with the substrate resistance can produce measurable effect at the main terminals of the devices. At frequencies low enough that we may ignore C_cb (open), the thermal noise of R_sub modulates the potential of the back gate, contributing some noisy drain current [8]:

f g KTR

i_nd² _,sub =4 _{sub mb}² ∆ Equation 2-6 Depending on bias conditions – and also on the magnitude of the effective substrate resistance and size of the back-gate transconductance – the noise generated by this mechanism may actually exceed the thermal noise contribution of the ordinary channel charge. In this regime, layout strategies that reduce the substrate resistance have a noticeable and beneficial effect on noise.

2

At frequencies well above the pole formed by C_cb and R_sub, however, the substrate thermal noise becomes unimportant, as is readily apparent from inspection of the physical structure and the corresponding frequency-dependent expression for the substrate noise contribution [8]:

C f

The characteristics of many IC processes are such that this pole is often around 1 GHz. Excess noise produced by this mechanism consequently will be most noticeable below about 1 GHz.

Drain Induced Gate Noise

In addition to drain noise, the thermal agitation of channel charge has another couples

capacitively into the gate terminal, leading to a noisy gate current (see figure 2.5).

Noisy gate current may also be produced by thermally noisy resistive gate material.

But this noise source will be separately discussed later, even though it is more and more important in nano-scale devices. Although the drain-induced-gate-noise is negligible at low frequencies, it can dominate at radio frequencies. Van der Ziel has shown that the drain-induced-gate-noise may be expressed as:

f

The circuit model for the drain-induced-gate-noise is a conductance connected between gate and source, shunted by a noise current source. This noise current clearly has a spectral density that is not constant. In fact, it increases with frequency, so perhaps it ought to be called “blue noise” to continue the optical analogy. Because the drain thermal current noise and the drain-induced-gate-noise do share a common origin, they are correlated. That is, there is a component of the gate noise current that is proportional to the drain noise current on an instantaneous basis.

Although the noise behavior of long-channel devices is fairly well understood,

the precise behavior of δ and γ in the short-channel regime is still unknown at present.

That’s why we have to do more research on the thermal noise of MOSFETs.

III. Process Simulation

Fig. 3.2 Output the structure of the 0.18µm MOSFETs by Taurus-Visual

A multi-finger RF MOSFETs is replaced with a conventional two-dimensional nMOSFETs to simplify the process simulation in this study. Figure 3.1 shows a

conventional MOSFETs. The final simulation structure shown in figure 3.2 would be similar to it. A 0.18 µm technology is used for this device with a gate oxide thickness of 4nm. The height of the gate is 0.16 µm and its length is 0.18 µm with a spacer of thickness 0.1 µm. The junction depth is 0.25 µm for source and drain. Titanium

silicide is used for the four contacts, gate, substrate, source and drain.

3.2 Process Model

Tsuprem4 offers various equations model to improve the fabrication process simulation. Model are offered to processes such as diffusion, ion implantation and oxidation, to improve the accuracy of the process. In this study, various models are used to improve the accuracy of the final device structure.

In this process simulation, three models are used. The first model, the PDFULL model, is used for the diffusion of arsenic and phosphorus impurities to reduce the lateral diffusion effect. The source and drain becomes connected under the gate region at the end of the fabrication without using this model. The TRANSIENT CLUSTER is used to take into the consideration of the transient enhanced diffusion experienced by the dopants. The MONTE CARLO model is being used for the implantation of the LDD, source and drain. It gives a better prediction of the ion implantation process.

Through this model, the ions lose energy through nuclear scattering and interaction with the electrons of target atoms. This model is also used due to the reason for the lateral diffusion of source and drain dopants. With the help of these two models, the merging problem of the source and drain encountered previously is solved.

3.3 Mesh Setting

The TCAD program calculates the various parameters by dividing the device into many segments and solving the equation at the etch grid. After the desired mesh resolution has been achieved the mesh is modified to fit exactly to the given location of the region interface. Hence, a proper and correct mesh is important for accurate solution.

For the study, the final mesh for device is shown in Figure 3.3. It’s regrid setting by Taurus-Process. The mesh at the area under the gate is more closely packed, as this area is important for the transistor. Most of the activities or phenomenon occurs here such as depletion and inversion. It explains why the mesh here is most dense as compare to other areas. The other less important areas such as the lower part of the substrate and the extreme left and right side of the transistor, are less important.

Therefore, the mesh spacing is lager there. A proper mesh can improve the simulation time needed and the efficiency of the program enormously. Generally speaking, the method to follow the more important area of simulation chooses the higher density mesh.

Fig. 3.3 Output the mesh of the 0.18µm MOSFETs by Taurus-Visual

3.4 Process Steps

The recipe used in this simulation has been used to fabricate a RF MOSFET used for the study. A silicon substrate of boron doping concentration of 1.5×10¹⁵cm^-3 is used. This doping is chosen so that the substrate has a resistivity of 10Ωcm^-1. This is done so that the model will be fabricated as similar as possible to the actual device. A gate oxide of 4 nm is formed through deposition before the other processing steps. A double diffused p-well is then implanted. After which, an n-channel implant is done, followed by a threshold implant. The threshold voltage implant is adjusted to give the device a threshold voltage of 0.5V. A rapid thermal annealing (RTA) process is then done for the well. After deposition of polysilicon and the etching process, a polysilicon gate is formed depletion effect. Spacers around the gate are then formed using nitride through the process of deposition and etching.

This device is also fabricated with features that reduces short channel effects.

After the well annealing, a LDD is formed by an implant and RTA process of 10s.

This lightly doped drain reduces the effect of hot carriers by forming a less abrupt junction and therefore reduces the electric field around the drain region. Besides LDD, pocket implants are used to reduce the effects of punchthrough and drain induced barrier lowering (DIBL).

Finally, a double diffused heavily doped n⁺ drain and source is implanted,

followed by a RTA process of 5s. The final device has a junction depth of around 0.25 µm. Titanium is then deposited and followed by a thermal budget of 900℃ for 2s

to form titanium silicide contacts for the source, drain and gate. Etching is then done to remove away the excess titanium.

The above process is transformed into the input file for the process simulation.

For the input file of the process simulation, refer to Appendix A. The final structure is shown in Figure 3.3. Τhe substrate used for simulation is two dimensional which is 1µm by 1µm in size.

The doping profile along the vertical cut at the center of the device is shown in Figure 3.4. It shows a doping profile. At the channel region, the substrate is lightly doped, followed by a heavier doping near the S/D region. The profile represents that of a graded S/D junction formed by LDD rather than an abrupt one. This reduces the electric field near the S/D junction.

In As

P Net Doping

In As

P Net Doping

Fig. 3.4 The doping profile along the center of the device

IV. Modeling

4.1 Methodology

Taurus-Medici is a powerful device simulation program that can be used to simulate the behavior of MOSFETs and bipolar transistors and other semiconductor devices. Medici models the two-dimensional (2D) distributions of potential and carrier concentrations in a device. The program can be used to predict electrical characteristics for arbitrary bias conditions. This project requires only a 2D simulation of the electrical characteristic. In addition to electrical characteristics, we also use this program for noise analysis, which is needed in this project. Taurus-Medici is able to simulate the various electrical and thermal characteristic of devices. Circuit analysis is also available but only the DC and transient simulation can be used in circuit analysis mode.

The flow of the study is shown in figure 4.1. First, we use the Tsuprem-4 to simulate the process of 0.18 µm MOSFETs and output the (name).tif file which

contains the doping profile, device structure, initial mesh etc. In order to make the resolution converge, improve the efficiency of the program and add the quantum mechanical model, the file outputted by Tsuprem-4 is read in Taurus-Process to execute the Regrid command. Next, the result is read in the Taurus-Device or Medici.

They evaluates various parameters by solving three basic partial differential equations (PDE), namely the Poisson’s equation and the two continuity equations (electron and hole current continuity equations). However, before the program can solve the PDE, various conditions need to be given for the simulator to solve the equations. The program then solves the PDE (with the conditions given) by first making an initial guess and slowly converges to the solution. Normally, the Newton method is chosen for convergence purpose.

Finally, the device model developed by Tsuprem-4 and Medici can result the electrical characteristics and then we can extract the BSIM parameters by program Aurora. The primary purpose of Aurora is to extract model parameters for circuit simulators, such as SPICE. Given a set of measured or simulated device characteristics, it extracts model parameters that produce a least-squares fit to the data.

Taurus-Process Tsuprem-4

It’s for simulation the processing steps used in the manufacture of silicon integrated circuits and

It’s for simulation the processing steps used in the manufacture of silicon integrated circuits and

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