The scan-chain ordering problem is formulated as TSP problem and modified for 3D IC designs considering TSV constraints. A fast scan-chain ordering algorithm is developed, consisting of two stages: (1) initial solution computation; and (2) local refinement and constraint solving. To avoid high complexity of 3D optimization, we convert such a problem into a TSP problem and use a state-of-the-art algorithm, a multiple fragment heuristic, combined with a dynamic closest-pair data structure named FastPair to quickly derive a satisfactory initial solution. Two techniques, 3D planarization and 3D relaxation are also proposed to minimize the wire cost, (power cost or combined cost) and to relax the total number of TSVs in use, respectively.
Experimental results show that the proposed algorithm can achieve comparable (<3 percent difference) or even better performance than that from a GA method, resulting in run time speeds at least two-orders faster on all ISCAS’89 benchmark circuits when considering TSV constraints. Moreover, our algorithm is shown to successfully scale to multiple scan chains for large designs from [23]. Therefore, the proposed algorithm can be practically used for scan-chain ordering of 3D IC designs.
As a result, the contributions of this work can be summarized as:
• Formulate scan-chain ordering considering TSV constraints into a modified TSP problem.
• Propose a greedy algorithm for scan-chain ordering of 3D-IC designs to simultaneously minimize wire and power costs.
• Demonstrate that the proposed algorithm can be practically used while supporting multiple scan chains.
To achieve high-performance computing on embedded systems, three-dimensional (3D) multi-core processors have become a promising alternative where energy efficiency is crucial to its success. Many heuristics applying Dynamic Voltage and Frequency Scaling (DVFS) techniques were proposed for energy minimization. However, most of the previous works were built upon a fixed task-to-core mapping where many slack spaces can be further improved. Therefore, in this work, we propose two dynamic remapping strategies to enhance an energy-aware task-scheduling algorithm considering transmission cost.
The other issue in this work, we apply two dynamic task-to-core remapping strategies, DR and IDR, on top of a baseline task-scheduling algorithm from [41].
Experimental results show the solutions from the two task-to-core remapping strategies are more close to the ILP solution where IDR only has 2.54 percent difference. Besides, two proposed methods can run 300X to 11,000X faster than the ILP method. Our experiments also show that the energy-saving rate of the IDR method can achieve 16 percent higher than that of the baseline algorithm on average.
As a result, the scheduling algorithm with dynamic task-to-core remapping can result in more energy efficient scheduling than that with a fixed task-to-core mapping.
Based on such result, the scheduling algorithm with dynamic task-to-core remapping can result in more energy efficient scheduling than that with a fixed task-to-core mapping. We also implemented an ILP-based method for an optimal solution without considering the transmission costs between cores. The experimental results show IDR strategy can achieve comparable performance as the ILP and the energy-saving difference between IDR and ILP is only −2.54 percent on average.
However, in our future work, we would like to further validate our IDR strategy considering transmission costs between cores. Hence, the problem is formulated into Quadratic Programming (QP) and compared to the IDR solution considering the transmission costs between cores. However, the scalability problem of QP-based method is more sever with transmission costs. Therefore, scheduling with a larger task graph is implemented into Genetic Algorithm (GA) and also compared to our IDR solution.
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國科會補助計畫衍生研發成果推廣資料表
日期:2011/10/30
國科會補助計畫
計畫名稱: 子計畫五：應用在驗證與測試3D IC整合過程中以計算智慧為基礎的測試向量 產生方法(2/2)
計畫主持人: 溫宏斌
計畫編號: 99-2220-E-009-039- 學門領域: 晶片科技計畫--整合型學術研究 計畫
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99 年度專題研究計畫研究成果彙整表
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2. W.T. Chen, C.C. Chiang, 3D-MFH, University Booth, IEEE/ACM Design Automation Conference, 2011.
國科會補助專題研究計畫成果報告自評表
3.目前有四篇論文發表在國內會議中 (The 22nd VLSI Design / CAD Symposium 2 篇，2011 VLSI Test Technology Workshop)
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