A physically based tunneling model is constructed using an accurate description of the electron quantization in the confined inversion-layer. This model contains a modified Wentzel–Kramers–Brillouin (WKB) method for tunneling through the barrier, including the effects of an ultrathin interfacial layer. The physical model of the electron tunneling through high-K stacks has been built up and experimental reproduction has been consistently achieved.
Our electron tunneling model is applied to high-K stacks. This model is easy to realize and computationally efficient. The data from the other tunneling models published in the open literature is also presented to confirm the accuracy of our model.
From the model, the effect of high-K film will appear when the F-N tunneling begins to dominate in high gate voltage. As the gate voltage goes higher, because of the reduced barrier height of the high-K film, electrons will tunnel within the Fowler Nordheim regime instead of the direct tunneling regime. So it is important to find a high-K dielectric with a sufficient barrier height to reduce tunneling current in a wide range of gate voltages.
This model has evidenced its potential applications in enabling in-depth understanding of the different subbands in the confined inversion layer in affecting electron tunneling conduction. The high-K stacks tunneling simulator can apply to either metal gate or poly gate. The tunneling parameters and energy band diagram can be established by the data fitting. We can therefore capture the underlying gate tunneling mechanisms of electrons in high-K gate stacks.
But there are efforts needed to investigate for further, such the hole tunneling across the high-K gate stacks. Even the temperature effect may be significant and must be
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taken into account. In addition, the electron tunneling model which was built in this thesis is focused on the inversion condition. Its extension to the accumulation may be needed.
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References
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Fig. 1. The gate leakage current is composed of conductance electron tunneling current (ISD) and valence hole current (IB).
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Fig. 2. Gate current separation shows the conductance electron tunneling current is dominant the gate leakage current in inversion region.
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Fig. 3. Measured gate current versus gate voltage for T = 373K and T=300K of (a) TaC/HfSiON/IL gate stacks and (b) TiN/HfO2/IL gate stacks of nMOSFETs.
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0.5 1.0 1.5 2.0
101 102 103 104
dhigh-K/dT = 0x10-4 V/K dIL/dT = -5x10-4 V/K
TaC/HfSiON/SiON/p-Si Scatters: Experimental Data Line: Simulated Result
(I G(373K)-I G(300K))/I G(300K) (%)
VG (V)
Fig. 4. Comparison of simulated (line) gate current change of T = 373K with respect to T = 300K versus gate voltage with our measured current (scatters).
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Fig. 5. The energy band diagram schematically shown for the n+poly/SiO2/p-substrate system.
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0.2 0.4 0.6 0.8 1.0
10-1 100 101 102
Symbols: Exp.
Fitting by our simulator tox = 1.27 nm , ox = 3.9 0 , mox = 0.43 m0 ,ox = 3.15 eV Nsub = 6x1017 cm-3 , Npoly = 1x1020 cm-3 n+Poly / SiO2 / p-Si
VG (V) J G (A/cm2 )
Fig. 6. The measured gate current versus gate voltage and its fitting for n+poly gate MOSFETs.
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0.0 0.2 0.4 0.6 0.8 1.0 0.0
2.0x10-5 4.0x10-5 6.0x10-5 8.0x10-5 1.0x10-4
W = 10m L = 1 m
I D (A) VD = 0.025 V
Vth = 0.18655 V Symbols: Exp.
VG (V)
n+Poly / SiO2 / p-Si
Fig. 7. The measured drain currents versus gate voltage for n+poly gate MOSFETs.
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Fig. 8. The energy band diagram for the metal gate/high-K/interface layer/Si substrate system.
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Fig. 9. Three different cases for electron tunneling in varying gate voltage.
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Fig. 10. The demonstration of three different tunneling regions.
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Fig. 16. The fitting results by our model in comparison with the measured tunneling current in the literature [7]. The tunneling parameters are the same as
those in [7].
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Fig. 17. The measured capacitance versus gate voltage for two different gate stacks. And it is also shown the fitting lines.
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Fig. 18. The measured drain currents versus gate voltage for (a) TaC/HfSiON/IL and (b) TiN/HfO2/IL gate stacks.
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Fitting by our simulator tIL = 1 nm , thigh-k = 3 nm
Fitting by our simulator tIL = 1 nm , thigh-k = 1.6 nm
Fig. 19. Comparison of the measured and calculated gate currents versus gate voltage for (a) TaC/HfSiON/IL and (b) TiN/HfO2/IL gate stacks.