Conclusion

In this thesis, to achieve high decoding performance and low hardware cost real-time entropy decoding systems, a high-throughput and fully hardwired entropy decoder for H.264/AVC is proposed. Our proposed entropy decoder architecture makes six main contributions:

1) Unlike previous multi-symbol CAVLC decoding architecture, which only accelerate the decoding procedure of run_before symbols, our proposed CAVLC decoder can further elevate the throughput by applying the delay balanced two-level decoding (DBTLD) architecture that can decode two level symbols in one cycle and shortens the critical path delay by 21% in

comparison to the conventional approach of cascading two level decoders, and allows the maximum working frequency to be about 390 MHz.

2) To further accelerate decoding procedure, a skipping mechanism is proposed to remove redundant decoding processes and provide an early termination of current residual block decoding procedure. Moreover, in the CAVLC

decoding procedure, since only one of coeff_token, trailing_ones_sing_flag, level, total_zeros, and run_before decoding units is assigned to work in each cycle, idled units are turned off by functional gating to reduce power

consumption.

3) A fully hardwired CABAC decoder design which combines SE parsing with decoding is proposed. By taking advantage of the characteristics of SE parsing flow and bin distribution among SEs, we design a prediction-based

pipelined architecture to accelerate the CABAC decoding procedure without stall for most case. The prediction hit rate can achieve 96.78% in average and over 99% in high bit-rate coding.

4) Our proposed hybrid CM memory architecture not only avoids structural hazards caused by CM reading and writing but also reduces the hardware cost overhead significantly by 48.6% in comparison to the implementation of all register approach.

5) With the proposed mathematical transform method, the critical path delay of TSBAD engine is efficiently improved by 28% compared with the traditional TSBAD engine, and allows the maximum working frequency to be about 264 MHz. The throughput of the proposed CABAC decoder can achieve 451.4 Mbins/sec in average.

6) We extend our entropy decoder towards SVC extension of H.264/AVC. At the working frequency 135 MHz, our proposed entropy decoder can support 3 spatial layers, maximum resolution 1920x1080, 3 temporal layers,

maximum frame rate 60 fps, and 3 CGS quality layers real-time SVC decoding.

6.2 Future Work

High Efficiency Video Coding (HEVC), so-called H.265 is currently under development by Joint Collaborative Team on Video Coding (JCT-VC) of MPEG and VCEG. As a successor to H.264/AVC, HEVC is targeted at next-generation HDTV displays with Super Hi-Vision and aims to reduce bit-rate requirement by half in comparison to H.264/AVC. However the improved coding efficiency usually accompanies with the expense of increased computational complexity. As a result, to

achieve real-time coding system, further search for a hardware-friendly entropy coding algorithm is necessary.

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Biographical Notes

姓名：廖元歆 學歷：

高雄市立高雄高級中學 (2001/09 – 2004/06) 國立交通大學電機資訊學士班 (2004/09 – 2008/06) 國立交通大學電子研究所系統組 (2008/09 – 2010/08)

著作：

Yuan-Hsin Liao, Gwo-Long Li, and Tian-Sheuan Chang, “A High Throughput VLSI Design with Hybrid Memory Architecture for H.264/AVC CABAC Decoder, ” in proceeding of IEEE International Symposium on Circuit and System, pp. 2007-2010, May 2010.